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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 /* 00002 * Copyright (C) 2004 by Ole Reinhardt <ole.reinhardt@kernelconcepts.de>, 00003 * Kernelconcepts http://www.kernelconcepts.de 00004 * 00005 * Redistribution and use in source and binary forms, with or without 00006 * modification, are permitted provided that the following conditions 00007 * are met: 00008 * 00009 * 1. Redistributions of source code must retain the above copyright 00010 * notice, this list of conditions and the following disclaimer. 00011 * 2. Redistributions in binary form must reproduce the above copyright 00012 * notice, this list of conditions and the following disclaimer in the 00013 * documentation and/or other materials provided with the distribution. 00014 * 3. Neither the name of the copyright holders nor the names of 00015 * contributors may be used to endorse or promote products derived 00016 * from this software without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00019 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00020 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00021 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00022 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00023 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00024 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00025 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00026 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00027 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00028 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00029 * SUCH DAMAGE. 00030 * 00031 * For additional information see http://www.ethernut.de/ 00032 * 00033 */ 00034 00050 00051 #ifndef _SJA1000_H_ 00052 #define _SJA1000_H_ 00053 00054 #include <stdint.h> 00055 00056 //Register and bit definitions for the SJA1000 00057 00058 // address and bit definitions for the Mode & Control Register 00059 #define SJA1000_MODECTRL (*(volatile uint8_t*) (sja_base+0)) 00060 #define RM_RR_Bit 0x01 // reset mode (request) bit 00061 00062 #define LOM_Bit 0x02 // listen only mode bit 00063 #define STM_Bit 0x04 // self test mode bit 00064 #define AFM_Bit 0x08 // acceptance filter mode bit 00065 #define SM_Bit 0x10 // enter sleep mode bit 00066 00067 // address and bit definitions for the Interrupt Enable & Control Register 00068 #define SJA1000_IEN (*(volatile uint8_t*) (sja_base+4)) // PeliCAN mode 00069 #define RIE_Bit 0x01 // receive interrupt enable bit 00070 #define TIE_Bit 0x02 // transmit interrupt enable bit 00071 #define EIE_Bit 0x04 // error warning interrupt enable bit 00072 #define DOIE_Bit 0x08 // data overrun interrupt enable bit 00073 #define WUIE_Bit 0x10 // wake-up interrupt enable bit 00074 #define EPIE_Bit 0x20 // error passive interrupt enable bit 00075 #define ALIE_Bit 0x40 // arbitration lost interr. enable bit 00076 #define BEIE_Bit 0x80 // bus error interrupt enable bit 00077 00078 // address and bit definitions for the Command Register 00079 #define SJA1000_CMD (*(volatile uint8_t*) (sja_base+1)) 00080 #define TR_Bit 0x01 // transmission request bit 00081 #define AT_Bit 0x02 // abort transmission bit 00082 #define RRB_Bit 0x04 // release receive buffer bit 00083 #define CDO_Bit 0x08 // clear data overrun bit 00084 #define SRR_Bit 0x10 // self reception request bit 00085 00086 // address and bit definitions for the Status Register 00087 #define SJA1000_STATUS (*(volatile uint8_t*) (sja_base+2)) 00088 #define RBS_Bit 0x01 // receive buffer status bit 00089 #define DOS_Bit 0x02 // data overrun status bit 00090 #define TBS_Bit 0x04 // transmit buffer status bit 00091 #define TCS_Bit 0x08 // transmission complete status bit 00092 #define RS_Bit 0x10 // receive status bit 00093 #define TS_Bit 0x20 // transmit status bit 00094 #define ES_Bit 0x40 // error status bit 00095 #define BS_Bit 0x80 // bus status bit 00096 00097 // address and bit definitions for the Interrupt Register 00098 #define SJA1000_INT (*(volatile uint8_t*) (sja_base+3)) 00099 #define RI_Bit 0x01 // receive interrupt bit 00100 #define TI_Bit 0x02 // transmit interrupt bit 00101 #define EI_Bit 0x04 // error warning interrupt bit 00102 #define DOI_Bit 0x08 // data overrun interrupt bit 00103 #define WUI_Bit 0x10 // wake-up interrupt bit 00104 00105 #define EPI_Bit 0x20 // error passive interrupt bit 00106 #define ALI_Bit 0x40 // arbitration lost interrupt bit 00107 #define BEI_Bit 0x80 // bus error interrupt bit 00108 00109 // address and bit definitions for the Bus Timing Registers 00110 #define SJA1000_BT0 (*(volatile uint8_t*) (sja_base+6)) 00111 #define SJA1000_BT1 (*(volatile uint8_t*) (sja_base+7)) 00112 #define SAM_Bit 0x80 // sample mode bit 00113 // 1 == the bus is sampled 3 times 00114 // 0 == the bus is sampled once */ 00115 00116 // address and bit definitions for the Output Control Register 00117 #define SJA1000_OUTCTRL (*(volatile uint8_t*) (sja_base+8)) 00118 // OCMODE1, OCMODE0 00119 #define BiPhaseMode 0x00 // bi-phase output mode 00120 #define NormalMode 0x02 // normal output mode 00121 #define ClkOutMode 0x03 // clock output mode 00122 // output pin configuration for TX1 00123 #define OCPOL1_Bit 0x20 // output polarity control bit 00124 #define Tx1Float 0x00 // configured as float 00125 #define Tx1PullDn 0x40 // configured as pull-down 00126 #define Tx1PullUp 0x80 // configured as pull-up 00127 #define Tx1PshPull 0xC0 // configured as push/pull 00128 // output configuration for TX0 00129 #define OCPOLO_Bit 0x04 // output polarity control bit 00130 #define Tx0Float 0x00 // configured as float 00131 #define Tx0PullDn 0x08 // configured as pull-down 00132 #define Tx0PullUp 0x10 // configured as pull-up 00133 #define Tx0PshPull 0x18 // configured as push/pull 00134 00135 // address definitions of Acceptance Code & Mask Registers 00136 #define SJA1000_AC0 (*(volatile uint8_t*) (sja_base+16)) 00137 #define SJA1000_AC1 (*(volatile uint8_t*) (sja_base+17)) 00138 #define SJA1000_AC2 (*(volatile uint8_t*) (sja_base+18)) 00139 #define SJA1000_AC3 (*(volatile uint8_t*) (sja_base+19)) 00140 #define SJA1000_AM0 (*(volatile uint8_t*) (sja_base+20)) 00141 #define SJA1000_AM1 (*(volatile uint8_t*) (sja_base+21)) 00142 #define SJA1000_AM2 (*(volatile uint8_t*) (sja_base+22)) 00143 #define SJA1000_AM3 (*(volatile uint8_t*) (sja_base+23)) 00144 00145 // address definitions of the Rx-Buffer 00146 #define SJA1000_RxFrameInfo (*(volatile uint8_t*) (sja_base+16)) 00147 #define SJA1000_Rx1 (*(volatile uint8_t*) (sja_base+17)) 00148 #define SJA1000_Rx2 (*(volatile uint8_t*) (sja_base+18)) 00149 #define SJA1000_Rx3 (*(volatile uint8_t*) (sja_base+19)) 00150 #define SJA1000_Rx4 (*(volatile uint8_t*) (sja_base+20)) 00151 #define SJA1000_Rx5 (*(volatile uint8_t*) (sja_base+21)) 00152 #define SJA1000_Rx6 (*(volatile uint8_t*) (sja_base+22)) 00153 #define SJA1000_Rx7 (*(volatile uint8_t*) (sja_base+23)) 00154 #define SJA1000_Rx8 (*(volatile uint8_t*) (sja_base+24)) 00155 #define SJA1000_Rx9 (*(volatile uint8_t*) (sja_base+25)) 00156 #define SJA1000_Rx10 (*(volatile uint8_t*) (sja_base+26)) 00157 #define SJA1000_Rx11 (*(volatile uint8_t*) (sja_base+27)) 00158 #define SJA1000_Rx12 (*(volatile uint8_t*) (sja_base+28)) 00159 00160 // address definitions of the Tx-Buffer 00161 /* write only addresses */ 00162 #define TestReg (*(volatile uint8_t*) (sja_base+9)) 00163 00164 #define SJA1000_TxFrameInfo (*(volatile uint8_t*) (sja_base+16)) 00165 #define SJA1000_Tx1 (*(volatile uint8_t*) (sja_base+17)) 00166 #define SJA1000_Tx2 (*(volatile uint8_t*) (sja_base+18)) 00167 #define SJA1000_Tx3 (*(volatile uint8_t*) (sja_base+19)) 00168 #define SJA1000_Tx4 (*(volatile uint8_t*) (sja_base+20)) 00169 #define SJA1000_Tx5 (*(volatile uint8_t*) (sja_base+21)) 00170 #define SJA1000_Tx6 (*(volatile uint8_t*) (sja_base+22)) 00171 #define SJA1000_Tx7 (*(volatile uint8_t*) (sja_base+23)) 00172 #define SJA1000_Tx8 (*(volatile uint8_t*) (sja_base+24)) 00173 #define SJA1000_Tx9 (*(volatile uint8_t*) (sja_base+25)) 00174 #define SJA1000_Tx10 (*(volatile uint8_t*) (sja_base+26)) 00175 #define SJA1000_Tx11 (*(volatile uint8_t*) (sja_base+27)) 00176 #define SJA1000_Tx12 (*(volatile uint8_t*) (sja_base+28)) 00177 00178 /* read only addresses */ 00179 #define SJA1000_TxFrameInfoRd (*(volatile uint8_t*) (sja_base+96)) 00180 #define SJA1000_TxRd1 (*(volatile uint8_t*) (sja_base+97)) 00181 #define SJA1000_TxRd2 (*(volatile uint8_t*) (sja_base+98)) 00182 #define SJA1000_TxRd3 (*(volatile uint8_t*) (sja_base+99)) 00183 #define SJA1000_TxRd4 (*(volatile uint8_t*) (sja_base+100)) 00184 #define SJA1000_TxRd5 (*(volatile uint8_t*) (sja_base+101)) 00185 #define SJA1000_TxRd6 (*(volatile uint8_t*) (sja_base+102)) 00186 #define SJA1000_TxRd7 (*(volatile uint8_t*) (sja_base+103)) 00187 #define SJA1000_TxRd8 (*(volatile uint8_t*) (sja_base+104)) 00188 #define SJA1000_TxRd9 (*(volatile uint8_t*) (sja_base+105)) 00189 #define SJA1000_TxRd10 (*(volatile uint8_t*) (sja_base+106)) 00190 #define SJA1000_TxRd11 (*(volatile uint8_t*) (sja_base+107)) 00191 #define SJA1000_TxRd12 (*(volatile uint8_t*) (sja_base+108)) 00192 00193 // address definitions of Other Registers 00194 #define SJA1000_ArbLostCap (*(volatile uint8_t*) (sja_base+11)) 00195 #define SJA1000_ErrCodeCap (*(volatile uint8_t*) (sja_base+12)) 00196 #define SJA1000_ErrWarnLimit (*(volatile uint8_t*) (sja_base+13)) 00197 #define SJA1000_RxErrCount (*(volatile uint8_t*) (sja_base+14)) 00198 #define SJA1000_TxErrCount (*(volatile uint8_t*) (sja_base+15)) 00199 #define SJA1000_RxMsgCount (*(volatile uint8_t*) (sja_base+29)) 00200 #define SJA1000_RxBufStartAdr (*(volatile uint8_t*) (sja_base+30)) 00201 00202 // address and bit definitions for the Clock Divider Register 00203 #define SJA1000_CLK_DIV (*(volatile uint8_t*) (sja_base+31)) 00204 #define DivBy1 0x07 // CLKOUT = oscillator frequency 00205 #define DivBy2 0x00 // CLKOUT = 1/2 oscillator frequency 00206 #define ClkOff_Bit 0x08 // clock off bit, control of the CLK OUT pin 00207 #define RXINTEN_Bit 0x20 // pin TX1 used for receive interrupt 00208 #define CBP_Bit 0x40 // CAN comparator bypass control bit 00209 #define CANMode_Bit 0x80 // CAN mode definition bit 00210 #define ClkOutMode 0x03 // clock output mode 00211 00212 // output pin configuration for TX1 00213 #define OCPOL1_Bit 0x20 // output polarity control bit 00214 #define Tx1Float 0x00 // configured as float 00215 #define Tx1PullDn 0x40 // configured as pull-down 00216 #define Tx1PullUp 0x80 // configured as pull-up 00217 #define Tx1PshPull 0xC0 // configured as push/pull 00218 00219 // output pin configuration for TX0 00220 #define OCPOL0_Bit 0x04 // output polarity control bit 00221 #define Tx0Float 0x00 // configured as float 00222 #define Tx0PullDn 0x08 // configured as pull-down 00223 00224 // Some sample konstants 00225 00226 /* bus timing values for 00227 - bit-rate : 1 MBit/s 00228 - oscillator frequency : 16 MHz, 0,1% 00229 - maximum tolerated propagation delay : 623 ns 00230 - minimum requested propagation delay : 23 ns 00231 */ 00232 00233 #define Presc_MB_16 0x00 // baud rate prescaler : 1 00234 #define SJW_MB_16 0x00 // SJW : 1 00235 #define TSEG1_MB_16 0x04 // TSEG1 : 5 00236 #define TSEG2_MB_16 0x10 // TSEG2 : 2 00237 00238 00239 // Error codes 00240 00241 #define errCAN_INVALID_BAUD 7 00242 #define CAN_OK 0 00243 #define CAN_ERR 1 00244 #define CAN_INIT_SPEED_ERR 1 00245 #define CAN_NOT_INITIATED 1 00246 #define CAN_NOT_STARTED 1 00247 #define CAN_TXBUF_FULL 2 00248 #define CAN_RXBUF_EMPTY 2 00249 00250 // Flag bits 00251 00252 #define CAN_LOST_FRAME 0x01 00253 #define CAN_BUS_OFF 0x02 00254 00255 // Frame Flag bits 00256 00257 #define CAN_29 0x80 00258 #define CAN_RTR 0x40 00259 00260 #define ClrIntEnSJA 0x00 00261 00262 extern NUTDEVICE devSJA1000; 00263 00264 #endif 00265