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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 #ifndef _DEV_SBBIF0_H_ 00002 #define _DEV_SBBIF0_H_ 00003 /* 00004 * Copyright (C) 2007 by egnite Software GmbH. All rights reserved. 00005 * 00006 * Redistribution and use in source and binary forms, with or without 00007 * modification, are permitted provided that the following conditions 00008 * are met: 00009 * 00010 * 1. Redistributions of source code must retain the above copyright 00011 * notice, this list of conditions and the following disclaimer. 00012 * 2. Redistributions in binary form must reproduce the above copyright 00013 * notice, this list of conditions and the following disclaimer in the 00014 * documentation and/or other materials provided with the distribution. 00015 * 3. Neither the name of the copyright holders nor the names of 00016 * contributors may be used to endorse or promote products derived 00017 * from this software without specific prior written permission. 00018 * 00019 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00020 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00021 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00022 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00023 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00024 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00025 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00026 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00027 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00028 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00029 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00030 * SUCH DAMAGE. 00031 * 00032 * For additional information see http://www.ethernut.de/ 00033 */ 00034 00062 #include <cfg/arch/gpio.h> 00063 #include <stdint.h> 00064 00068 #ifndef SBBI0_MAX_DEVICES 00069 #define SBBI0_MAX_DEVICES 4 00070 #endif 00071 00072 #if defined(__AVR__) /* MCU */ 00073 /* 00074 * AVR implementation. 00075 * ====================================== 00076 */ 00077 00078 #ifdef SBBI0_CS0_BIT 00079 00080 #if (SBBI0_CS0_PORT == AVRPORTB) 00081 #define SBBI0_CS0_SOD_REG PORTB 00082 #define SBBI0_CS0_OE_REG DDRB 00083 #elif (SBBI0_CS0_PORT == AVRPORTD) 00084 #define SBBI0_CS0_SOD_REG PORTD 00085 #define SBBI0_CS0_OE_REG DDRD 00086 #elif (SBBI0_CS0_PORT == AVRPORTE) 00087 #define SBBI0_CS0_SOD_REG PORTE 00088 #define SBBI0_CS0_OE_REG DDRE 00089 #elif (SBBI0_CS0_PORT == AVRPORTF) 00090 #define SBBI0_CS0_SOD_REG PORTF 00091 #define SBBI0_CS0_OE_REG DDRF 00092 #elif (SBBI0_CS0_PORT == AVRPORTG) 00093 #define SBBI0_CS0_SOD_REG PORTG 00094 #define SBBI0_CS0_OE_REG DDRG 00095 #elif (SBBI0_CS0_PORT == AVRPORTH) 00096 #define SBBI0_CS0_SOD_REG PORTH 00097 #define SBBI0_CS0_OE_REG DDRH 00098 #endif 00099 00101 #define SBBI0_CS0_ENA() sbi(SBBI0_CS0_OE_REG, SBBI0_CS0_BIT) 00102 00103 #define SBBI0_CS0_CLR() cbi(SBBI0_CS0_SOD_REG, SBBI0_CS0_BIT) 00104 00105 #define SBBI0_CS0_SET() sbi(SBBI0_CS0_SOD_REG, SBBI0_CS0_BIT) 00106 00107 #else /* SBBI0_CS0_BIT */ 00108 00109 #define SBBI0_CS0_ENA() 00110 #define SBBI0_CS0_CLR() 00111 #define SBBI0_CS0_SET() 00112 00113 #endif /* SBBI0_CS0_BIT */ 00114 00115 #ifdef SBBI0_CS1_BIT 00116 00117 #if (SBBI0_CS1_PORT == AVRPORTB) 00118 #define SBBI0_CS1_SOD_REG PORTB 00119 #define SBBI0_CS1_OE_REG DDRB 00120 #elif (SBBI0_CS1_PORT == AVRPORTD) 00121 #define SBBI0_CS1_SOD_REG PORTD 00122 #define SBBI0_CS1_OE_REG DDRD 00123 #elif (SBBI0_CS1_PORT == AVRPORTE) 00124 #define SBBI0_CS1_SOD_REG PORTE 00125 #define SBBI0_CS1_OE_REG DDRE 00126 #elif (SBBI0_CS1_PORT == AVRPORTF) 00127 #define SBBI0_CS1_SOD_REG PORTF 00128 #define SBBI0_CS1_OE_REG DDRF 00129 #elif (SBBI0_CS1_PORT == AVRPORTG) 00130 #define SBBI0_CS1_SOD_REG PORTG 00131 #define SBBI0_CS1_OE_REG DDRG 00132 #elif (SBBI0_CS1_PORT == AVRPORTH) 00133 #define SBBI0_CS1_SOD_REG PORTH 00134 #define SBBI0_CS1_OE_REG DDRH 00135 #endif 00136 00138 #define SBBI0_CS1_ENA() sbi(SBBI0_CS1_OE_REG, SBBI0_CS1_BIT) 00139 00140 #define SBBI0_CS1_CLR() cbi(SBBI0_CS1_SOD_REG, SBBI0_CS1_BIT) 00141 00142 #define SBBI0_CS1_SET() sbi(SBBI0_CS1_SOD_REG, SBBI0_CS1_BIT) 00143 00144 #else /* SBBI0_CS1_BIT */ 00145 00146 #define SBBI0_CS1_ENA() 00147 #define SBBI0_CS1_CLR() 00148 #define SBBI0_CS1_SET() 00149 00150 #endif /* SBBI0_CS1_BIT */ 00151 00152 #ifdef SBBI0_CS2_BIT 00153 00154 #if (SBBI0_CS2_PORT == AVRPORTB) 00155 #define SBBI0_CS2_SOD_REG PORTB 00156 #define SBBI0_CS2_OE_REG DDRB 00157 #elif (SBBI0_CS2_PORT == AVRPORTD) 00158 #define SBBI0_CS2_SOD_REG PORTD 00159 #define SBBI0_CS2_OE_REG DDRD 00160 #elif (SBBI0_CS2_PORT == AVRPORTE) 00161 #define SBBI0_CS2_SOD_REG PORTE 00162 #define SBBI0_CS2_OE_REG DDRE 00163 #elif (SBBI0_CS2_PORT == AVRPORTF) 00164 #define SBBI0_CS2_SOD_REG PORTF 00165 #define SBBI0_CS2_OE_REG DDRF 00166 #elif (SBBI0_CS2_PORT == AVRPORTG) 00167 #define SBBI0_CS2_SOD_REG PORTG 00168 #define SBBI0_CS2_OE_REG DDRG 00169 #elif (SBBI0_CS2_PORT == AVRPORTH) 00170 #define SBBI0_CS2_SOD_REG PORTH 00171 #define SBBI0_CS2_OE_REG DDRH 00172 #endif 00173 00175 #define SBBI0_CS2_ENA() sbi(SBBI0_CS2_OE_REG, SBBI0_CS2_BIT) 00176 00177 #define SBBI0_CS2_CLR() cbi(SBBI0_CS2_SOD_REG, SBBI0_CS2_BIT) 00178 00179 #define SBBI0_CS2_SET() sbi(SBBI0_CS2_SOD_REG, SBBI0_CS2_BIT) 00180 00181 #else /* SBBI0_CS2_BIT */ 00182 00183 #define SBBI0_CS2_ENA() 00184 #define SBBI0_CS2_CLR() 00185 #define SBBI0_CS2_SET() 00186 00187 #endif /* SBBI0_CS2_BIT */ 00188 00189 #ifdef SBBI0_CS3_BIT 00190 00191 #if (SBBI0_CS3_PORT == AVRPORTB) 00192 #define SBBI0_CS3_SOD_REG PORTB 00193 #define SBBI0_CS3_OE_REG DDRB 00194 #elif (SBBI0_CS3_PORT == AVRPORTD) 00195 #define SBBI0_CS3_SOD_REG PORTD 00196 #define SBBI0_CS3_OE_REG DDRD 00197 #elif (SBBI0_CS3_PORT == AVRPORTE) 00198 #define SBBI0_CS3_SOD_REG PORTE 00199 #define SBBI0_CS3_OE_REG DDRE 00200 #elif (SBBI0_CS3_PORT == AVRPORTF) 00201 #define SBBI0_CS3_SOD_REG PORTF 00202 #define SBBI0_CS3_OE_REG DDRF 00203 #elif (SBBI0_CS3_PORT == AVRPORTG) 00204 #define SBBI0_CS3_SOD_REG PORTG 00205 #define SBBI0_CS3_OE_REG DDRG 00206 #elif (SBBI0_CS3_PORT == AVRPORTH) 00207 #define SBBI0_CS3_SOD_REG PORTH 00208 #define SBBI0_CS3_OE_REG DDRH 00209 #endif 00210 00212 #define SBBI0_CS3_ENA() sbi(SBBI0_CS3_OE_REG, SBBI0_CS3_BIT) 00213 00214 #define SBBI0_CS3_CLR() cbi(SBBI0_CS3_SOD_REG, SBBI0_CS3_BIT) 00215 00216 #define SBBI0_CS3_SET() sbi(SBBI0_CS3_SOD_REG, SBBI0_CS3_BIT) 00217 00218 #else /* SBBI0_CS3_BIT */ 00219 00220 #define SBBI0_CS3_ENA() 00221 #define SBBI0_CS3_CLR() 00222 #define SBBI0_CS3_SET() 00223 00224 #endif /* SBBI0_CS3_BIT */ 00225 00226 #ifdef SBBI0_RST0_BIT 00227 00228 #if (SBBI0_RST0_PORT == AVRPORTB) 00229 #define SBBI0_RST0_SOD_REG PORTB 00230 #define SBBI0_RST0_OE_REG DDRB 00231 #elif (SBBI0_RST0_PORT == AVRPORTD) 00232 #define SBBI0_RST0_SOD_REG PORTD 00233 #define SBBI0_RST0_OE_REG DDRD 00234 #elif (SBBI0_RST0_PORT == AVRPORTE) 00235 #define SBBI0_RST0_SOD_REG PORTE 00236 #define SBBI0_RST0_OE_REG DDRE 00237 #elif (SBBI0_RST0_PORT == AVRPORTF) 00238 #define SBBI0_RST0_SOD_REG PORTF 00239 #define SBBI0_RST0_OE_REG DDRF 00240 #elif (SBBI0_RST0_PORT == AVRPORTG) 00241 #define SBBI0_RST0_SOD_REG PORTG 00242 #define SBBI0_RST0_OE_REG DDRG 00243 #elif (SBBI0_RST0_PORT == AVRPORTH) 00244 #define SBBI0_RST0_SOD_REG PORTH 00245 #define SBBI0_RST0_OE_REG DDRH 00246 #endif 00247 00249 #define SBBI0_RST0_ENA() sbi(SBBI0_RST0_OE_REG, SBBI0_RST0_BIT) 00250 00251 #define SBBI0_RST0_CLR() cbi(SBBI0_RST0_SOD_REG, SBBI0_RST0_BIT) 00252 00253 #define SBBI0_RST0_SET() sbi(SBBI0_RST0_SOD_REG, SBBI0_RST0_BIT) 00254 00255 #else /* SBBI0_RST0_BIT */ 00256 00257 #define SBBI0_RST0_ENA() 00258 #define SBBI0_RST0_CLR() 00259 #define SBBI0_RST0_SET() 00260 00261 #endif /* SBBI0_RST0_BIT */ 00262 00263 #ifdef SBBI0_RST1_BIT 00264 00265 #if (SBBI0_RST1_PORT == AVRPORTB) 00266 #define SBBI0_RST1_SOD_REG PORTB 00267 #define SBBI0_RST1_OE_REG DDRB 00268 #elif (SBBI0_RST1_PORT == AVRPORTD) 00269 #define SBBI0_RST1_SOD_REG PORTD 00270 #define SBBI0_RST1_OE_REG DDRD 00271 #elif (SBBI0_RST1_PORT == AVRPORTE) 00272 #define SBBI0_RST1_SOD_REG PORTE 00273 #define SBBI0_RST1_OE_REG DDRE 00274 #elif (SBBI0_RST1_PORT == AVRPORTF) 00275 #define SBBI0_RST1_SOD_REG PORTF 00276 #define SBBI0_RST1_OE_REG DDRF 00277 #elif (SBBI0_RST1_PORT == AVRPORTG) 00278 #define SBBI0_RST1_SOD_REG PORTG 00279 #define SBBI0_RST1_OE_REG DDRG 00280 #elif (SBBI0_RST1_PORT == AVRPORTH) 00281 #define SBBI0_RST1_SOD_REG PORTH 00282 #define SBBI0_RST1_OE_REG DDRH 00283 #endif 00284 00286 #define SBBI0_RST1_ENA() sbi(SBBI0_RST1_OE_REG, SBBI0_RST1_BIT) 00287 00288 #define SBBI0_RST1_CLR() cbi(SBBI0_RST1_SOD_REG, SBBI0_RST1_BIT) 00289 00290 #define SBBI0_RST1_SET() sbi(SBBI0_RST1_SOD_REG, SBBI0_RST1_BIT) 00291 00292 #else /* SBBI0_RST1_BIT */ 00293 00294 #define SBBI0_RST1_ENA() 00295 #define SBBI0_RST1_CLR() 00296 #define SBBI0_RST1_SET() 00297 00298 #endif /* SBBI0_RST1_BIT */ 00299 00300 #ifdef SBBI0_RST2_BIT 00301 00302 #if (SBBI0_RST2_PORT == AVRPORTB) 00303 #define SBBI0_RST2_SOD_REG PORTB 00304 #define SBBI0_RST2_OE_REG DDRB 00305 #elif (SBBI0_RST2_PORT == AVRPORTD) 00306 #define SBBI0_RST2_SOD_REG PORTD 00307 #define SBBI0_RST2_OE_REG DDRD 00308 #elif (SBBI0_RST2_PORT == AVRPORTE) 00309 #define SBBI0_RST2_SOD_REG PORTE 00310 #define SBBI0_RST2_OE_REG DDRE 00311 #elif (SBBI0_RST2_PORT == AVRPORTF) 00312 #define SBBI0_RST2_SOD_REG PORTF 00313 #define SBBI0_RST2_OE_REG DDRF 00314 #elif (SBBI0_RST2_PORT == AVRPORTG) 00315 #define SBBI0_RST2_SOD_REG PORTG 00316 #define SBBI0_RST2_OE_REG DDRG 00317 #elif (SBBI0_RST2_PORT == AVRPORTH) 00318 #define SBBI0_RST2_SOD_REG PORTH 00319 #define SBBI0_RST2_OE_REG DDRH 00320 #endif 00321 00323 #define SBBI0_RST2_ENA() sbi(SBBI0_RST2_OE_REG, SBBI0_RST2_BIT) 00324 00325 #define SBBI0_RST2_CLR() cbi(SBBI0_RST2_SOD_REG, SBBI0_RST2_BIT) 00326 00327 #define SBBI0_RST2_SET() sbi(SBBI0_RST2_SOD_REG, SBBI0_RST2_BIT) 00328 00329 #else /* SBBI0_RST2_BIT */ 00330 00331 #define SBBI0_RST2_ENA() 00332 #define SBBI0_RST2_CLR() 00333 #define SBBI0_RST2_SET() 00334 00335 #endif /* SBBI0_RST2_BIT */ 00336 00337 #ifdef SBBI0_RST3_BIT 00338 00339 #if (SBBI0_RST3_PORT == AVRPORTB) 00340 #define SBBI0_RST3_SOD_REG PORTB 00341 #define SBBI0_RST3_OE_REG DDRB 00342 #elif (SBBI0_RST3_PORT == AVRPORTD) 00343 #define SBBI0_RST3_SOD_REG PORTD 00344 #define SBBI0_RST3_OE_REG DDRD 00345 #elif (SBBI0_RST3_PORT == AVRPORTE) 00346 #define SBBI0_RST3_SOD_REG PORTE 00347 #define SBBI0_RST3_OE_REG DDRE 00348 #elif (SBBI0_RST3_PORT == AVRPORTF) 00349 #define SBBI0_RST3_SOD_REG PORTF 00350 #define SBBI0_RST3_OE_REG DDRF 00351 #elif (SBBI0_RST3_PORT == AVRPORTG) 00352 #define SBBI0_RST3_SOD_REG PORTG 00353 #define SBBI0_RST3_OE_REG DDRG 00354 #elif (SBBI0_RST3_PORT == AVRPORTH) 00355 #define SBBI0_RST3_SOD_REG PORTH 00356 #define SBBI0_RST3_OE_REG DDRH 00357 #endif 00358 00360 #define SBBI0_RST3_ENA() sbi(SBBI0_RST3_OE_REG, SBBI0_RST3_BIT) 00361 00362 #define SBBI0_RST3_CLR() cbi(SBBI0_RST3_SOD_REG, SBBI0_RST3_BIT) 00363 00364 #define SBBI0_RST3_SET() sbi(SBBI0_RST3_SOD_REG, SBBI0_RST3_BIT) 00365 00366 #else /* SBBI0_RST3_BIT */ 00367 00368 #define SBBI0_RST3_ENA() 00369 #define SBBI0_RST3_CLR() 00370 #define SBBI0_RST3_SET() 00371 00372 #endif /* SBBI0_RST3_BIT */ 00373 00374 #ifdef SBBI0_SCK_BIT 00375 00376 #if (SBBI0_SCK_PORT == AVRPORTB) 00377 #define SBBI0_SCK_SOD_REG PORTB 00378 #define SBBI0_SCK_OE_REG DDRB 00379 #elif (SBBI0_SCK_PORT == AVRPORTD) 00380 #define SBBI0_SCK_SOD_REG PORTD 00381 #define SBBI0_SCK_OE_REG DDRD 00382 #elif (SBBI0_SCK_PORT == AVRPORTE) 00383 #define SBBI0_SCK_SOD_REG PORTE 00384 #define SBBI0_SCK_OE_REG DDRE 00385 #elif (SBBI0_SCK_PORT == AVRPORTF) 00386 #define SBBI0_SCK_SOD_REG PORTF 00387 #define SBBI0_SCK_OE_REG DDRF 00388 #elif (SBBI0_SCK_PORT == AVRPORTG) 00389 #define SBBI0_SCK_SOD_REG PORTG 00390 #define SBBI0_SCK_OE_REG DDRG 00391 #elif (SBBI0_SCK_PORT == AVRPORTH) 00392 #define SBBI0_SCK_SOD_REG PORTH 00393 #define SBBI0_SCK_OE_REG DDRH 00394 #endif 00395 00397 #define SBBI0_SCK_ENA() sbi(SBBI0_SCK_OE_REG, SBBI0_SCK_BIT) 00398 00399 #define SBBI0_SCK_CLR() cbi(SBBI0_SCK_SOD_REG, SBBI0_SCK_BIT) 00400 00401 #define SBBI0_SCK_SET() sbi(SBBI0_SCK_SOD_REG, SBBI0_SCK_BIT) 00402 00403 #if defined(SBBI0_MOSI_BIT) 00404 00405 #if (SBBI0_MOSI_PORT == AVRPORTB) 00406 #define SBBI0_MOSI_SOD_REG PORTB 00407 #define SBBI0_MOSI_OE_REG DDRB 00408 #elif (SBBI0_MOSI_PORT == AVRPORTD) 00409 #define SBBI0_MOSI_SOD_REG PORTD 00410 #define SBBI0_MOSI_OE_REG DDRD 00411 #elif (SBBI0_MOSI_PORT == AVRPORTE) 00412 #define SBBI0_MOSI_SOD_REG PORTE 00413 #define SBBI0_MOSI_OE_REG DDRE 00414 #elif (SBBI0_MOSI_PORT == AVRPORTF) 00415 #define SBBI0_MOSI_SOD_REG PORTF 00416 #define SBBI0_MOSI_OE_REG DDRF 00417 #elif (SBBI0_MOSI_PORT == AVRPORTG) 00418 #define SBBI0_MOSI_SOD_REG PORTG 00419 #define SBBI0_MOSI_OE_REG DDRG 00420 #elif (SBBI0_MOSI_PORT == AVRPORTH) 00421 #define SBBI0_MOSI_SOD_REG PORTH 00422 #define SBBI0_MOSI_OE_REG DDRH 00423 #endif 00424 00426 #define SBBI0_MOSI_ENA() sbi(SBBI0_MOSI_OE_REG, SBBI0_MOSI_BIT) 00427 00428 #define SBBI0_MOSI_CLR() cbi(SBBI0_MOSI_SOD_REG, SBBI0_MOSI_BIT) 00429 00430 #define SBBI0_MOSI_SET() sbi(SBBI0_MOSI_SOD_REG, SBBI0_MOSI_BIT) 00431 00432 #else /* SBBI0_MOSI_BIT */ 00433 00434 #define SBBI0_MOSI_ENA() 00435 #define SBBI0_MOSI_CLR() 00436 #define SBBI0_MOSI_SET() 00437 00438 #endif /* SBBI0_MOSI_BIT */ 00439 00440 #if defined(SBBI0_MISO_BIT) 00441 00442 #if (SBBI0_MISO_PORT == AVRPORTB) 00443 #define SBBI0_MISO_PDS_REG PINB 00444 #define SBBI0_MISO_PUE_REG PORTB 00445 #define SBBI0_MISO_OE_REG DDRB 00446 #elif (SBBI0_MISO_PORT == AVRPORTD) 00447 #define SBBI0_MISO_PDS_REG PIND 00448 #define SBBI0_MISO_PUE_REG PORTD 00449 #define SBBI0_MISO_OE_REG DDRD 00450 #elif (SBBI0_MISO_PORT == AVRPORTE) 00451 #define SBBI0_MISO_PDS_REG PINE 00452 #define SBBI0_MISO_PUE_REG PORTE 00453 #define SBBI0_MISO_OE_REG DDRE 00454 #elif (SBBI0_MISO_PORT == AVRPORTF) 00455 #define SBBI0_MISO_PDS_REG PINF 00456 #define SBBI0_MISO_PUE_REG PORTF 00457 #define SBBI0_MISO_OE_REG DDRF 00458 #elif (SBBI0_MISO_PORT == AVRPORTG) 00459 #define SBBI0_MISO_PDS_REG PING 00460 #define SBBI0_MISO_PUE_REG PORTG 00461 #define SBBI0_MISO_OE_REG DDRG 00462 #elif (SBBI0_MISO_PORT == AVRPORTH) 00463 #define SBBI0_MISO_PDS_REG PINH 00464 #define SBBI0_MISO_PUE_REG PORTH 00465 #define SBBI0_MISO_OE_REG DDRH 00466 #endif 00467 00469 #define SBBI0_MISO_ENA() \ 00470 cbi(SBBI0_MISO_OE_REG, SBBI0_MISO_BIT); \ 00471 sbi(SBBI0_MISO_PUE_REG, SBBI0_MISO_BIT) 00472 00473 #define SBBI0_MISO_TST() ((inb(SBBI0_MISO_PDS_REG) & _BV(SBBI0_MISO_BIT)) == _BV(SBBI0_MISO_BIT)) 00474 00475 #else /* SBBI0_MISO_BIT */ 00476 00477 #define SBBI0_MISO_ENA() 00478 #define SBBI0_MISO_TST() 0 00479 00480 #endif /* SBBI0_MISO_BIT */ 00481 00482 #else /* SBBI0_SCK_BIT */ 00483 00484 #define SBBI0_SCK_ENA() 00485 #define SBBI0_SCK_CLR() 00486 #define SBBI0_SCK_SET() 00487 00488 #define SBBI0_MOSI_ENA() 00489 #define SBBI0_MOSI_CLR() 00490 #define SBBI0_MOSI_SET() 00491 00492 #define SBBI0_MISO_ENA() 00493 #define SBBI0_MISO_TST() 0 00494 00495 #endif /* SBBI0_SCK_BIT */ 00496 00497 #else /* MCU */ 00498 /* 00499 * AT91 implementation. 00500 * ====================================== 00501 */ 00502 00503 #ifdef SBBI0_CS0_BIT 00504 00505 #ifndef SBBI0_CS0_PORT 00506 #define SBBI0_CS0_PORT NUTGPIO_PORT 00507 #endif 00508 00509 #if SBBI0_CS0_PORT == NUTGPIO_PORT 00510 #define SBBI0_CS0_PE_REG PIO_PER 00511 #define SBBI0_CS0_OE_REG PIO_OER 00512 #define SBBI0_CS0_COD_REG PIO_CODR 00513 #define SBBI0_CS0_SOD_REG PIO_SODR 00514 #elif SBBI0_CS0_PORT == NUTGPIO_PORTA 00515 #define SBBI0_CS0_PE_REG PIOA_PER 00516 #define SBBI0_CS0_OE_REG PIOA_OER 00517 #define SBBI0_CS0_COD_REG PIOA_CODR 00518 #define SBBI0_CS0_SOD_REG PIOA_SODR 00519 #elif SBBI0_CS0_PORT == NUTGPIO_PORTB 00520 #define SBBI0_CS0_PE_REG PIOB_PER 00521 #define SBBI0_CS0_OE_REG PIOB_OER 00522 #define SBBI0_CS0_COD_REG PIOB_CODR 00523 #define SBBI0_CS0_SOD_REG PIOB_SODR 00524 #elif SBBI0_CS0_PORT == NUTGPIO_PORTC 00525 #define SBBI0_CS0_PE_REG PIOC_PER 00526 #define SBBI0_CS0_OE_REG PIOC_OER 00527 #define SBBI0_CS0_COD_REG PIOC_CODR 00528 #define SBBI0_CS0_SOD_REG PIOC_SODR 00529 #endif 00530 00532 #define SBBI0_CS0_ENA() \ 00533 outr(SBBI0_CS0_PE_REG, _BV(SBBI0_CS0_BIT)); \ 00534 outr(SBBI0_CS0_OE_REG, _BV(SBBI0_CS0_BIT)) 00535 00536 #define SBBI0_CS0_CLR() outr(SBBI0_CS0_COD_REG, _BV(SBBI0_CS0_BIT)) 00537 00538 #define SBBI0_CS0_SET() outr(SBBI0_CS0_SOD_REG, _BV(SBBI0_CS0_BIT)) 00539 00540 #else /* SBBI0_CS0_BIT */ 00541 00542 #define SBBI0_CS0_ENA() 00543 #define SBBI0_CS0_CLR() 00544 #define SBBI0_CS0_SET() 00545 00546 #endif /* SBBI0_CS0_BIT */ 00547 00548 #ifdef SBBI0_CS1_BIT 00549 00550 #ifndef SBBI0_CS1_PORT 00551 #define SBBI0_CS1_PORT NUTGPIO_PORT 00552 #endif 00553 00554 #if SBBI0_CS1_PORT == NUTGPIO_PORT 00555 #define SBBI0_CS1_PE_REG PIO_PER 00556 #define SBBI0_CS1_OE_REG PIO_OER 00557 #define SBBI0_CS1_COD_REG PIO_CODR 00558 #define SBBI0_CS1_SOD_REG PIO_SODR 00559 #elif SBBI0_CS1_PORT == NUTGPIO_PORTA 00560 #define SBBI0_CS1_PE_REG PIOA_PER 00561 #define SBBI0_CS1_OE_REG PIOA_OER 00562 #define SBBI0_CS1_COD_REG PIOA_CODR 00563 #define SBBI0_CS1_SOD_REG PIOA_SODR 00564 #elif SBBI0_CS1_PORT == NUTGPIO_PORTB 00565 #define SBBI0_CS1_PE_REG PIOB_PER 00566 #define SBBI0_CS1_OE_REG PIOB_OER 00567 #define SBBI0_CS1_COD_REG PIOB_CODR 00568 #define SBBI0_CS1_SOD_REG PIOB_SODR 00569 #elif SBBI0_CS1_PORT == NUTGPIO_PORTC 00570 #define SBBI0_CS1_PE_REG PIOC_PER 00571 #define SBBI0_CS1_OE_REG PIOC_OER 00572 #define SBBI0_CS1_COD_REG PIOC_CODR 00573 #define SBBI0_CS1_SOD_REG PIOC_SODR 00574 #endif 00575 00577 #define SBBI0_CS1_ENA() \ 00578 outr(SBBI0_CS1_PE_REG, _BV(SBBI0_CS1_BIT)); \ 00579 outr(SBBI0_CS1_OE_REG, _BV(SBBI0_CS1_BIT)) 00580 00581 #define SBBI0_CS1_CLR() outr(SBBI0_CS1_COD_REG, _BV(SBBI0_CS1_BIT)) 00582 00583 #define SBBI0_CS1_SET() outr(SBBI0_CS1_SOD_REG, _BV(SBBI0_CS1_BIT)) 00584 00585 #else /* SBBI0_CS1_BIT */ 00586 00587 #define SBBI0_CS1_ENA() 00588 #define SBBI0_CS1_CLR() 00589 #define SBBI0_CS1_SET() 00590 00591 #endif /* SBBI0_CS1_BIT */ 00592 00593 #ifdef SBBI0_CS2_BIT 00594 00595 #ifndef SBBI0_CS2_PORT 00596 #define SBBI0_CS2_PORT NUTGPIO_PORT 00597 #endif 00598 00599 #if SBBI0_CS2_PORT == NUTGPIO_PORT 00600 #define SBBI0_CS2_PE_REG PIO_PER 00601 #define SBBI0_CS2_OE_REG PIO_OER 00602 #define SBBI0_CS2_COD_REG PIO_CODR 00603 #define SBBI0_CS2_SOD_REG PIO_SODR 00604 #elif SBBI0_CS2_PORT == NUTGPIO_PORTA 00605 #define SBBI0_CS2_PE_REG PIOA_PER 00606 #define SBBI0_CS2_OE_REG PIOA_OER 00607 #define SBBI0_CS2_COD_REG PIOA_CODR 00608 #define SBBI0_CS2_SOD_REG PIOA_SODR 00609 #elif SBBI0_CS2_PORT == NUTGPIO_PORTB 00610 #define SBBI0_CS2_PE_REG PIOB_PER 00611 #define SBBI0_CS2_OE_REG PIOB_OER 00612 #define SBBI0_CS2_COD_REG PIOB_CODR 00613 #define SBBI0_CS2_SOD_REG PIOB_SODR 00614 #elif SBBI0_CS2_PORT == NUTGPIO_PORTC 00615 #define SBBI0_CS2_PE_REG PIOC_PER 00616 #define SBBI0_CS2_OE_REG PIOC_OER 00617 #define SBBI0_CS2_COD_REG PIOC_CODR 00618 #define SBBI0_CS2_SOD_REG PIOC_SODR 00619 #endif 00620 00622 #define SBBI0_CS2_ENA() \ 00623 outr(SBBI0_CS2_PE_REG, _BV(SBBI0_CS2_BIT)); \ 00624 outr(SBBI0_CS2_OE_REG, _BV(SBBI0_CS2_BIT)) 00625 00626 #define SBBI0_CS2_CLR() outr(SBBI0_CS2_COD_REG, _BV(SBBI0_CS2_BIT)) 00627 00628 #define SBBI0_CS2_SET() outr(SBBI0_CS2_SOD_REG, _BV(SBBI0_CS2_BIT)) 00629 00630 #else /* SBBI0_CS2_BIT */ 00631 00632 #define SBBI0_CS2_ENA() 00633 #define SBBI0_CS2_CLR() 00634 #define SBBI0_CS2_SET() 00635 00636 #endif /* SBBI0_CS2_BIT */ 00637 00638 #ifdef SBBI0_CS3_BIT 00639 00640 #ifndef SBBI0_CS3_PORT 00641 #define SBBI0_CS3_PORT NUTGPIO_PORT 00642 #endif 00643 00644 #if SBBI0_CS3_PORT == NUTGPIO_PORT 00645 #define SBBI0_CS3_PE_REG PIO_PER 00646 #define SBBI0_CS3_OE_REG PIO_OER 00647 #define SBBI0_CS3_COD_REG PIO_CODR 00648 #define SBBI0_CS3_SOD_REG PIO_SODR 00649 #elif SBBI0_CS3_PORT == NUTGPIO_PORTA 00650 #define SBBI0_CS3_PE_REG PIOA_PER 00651 #define SBBI0_CS3_OE_REG PIOA_OER 00652 #define SBBI0_CS3_COD_REG PIOA_CODR 00653 #define SBBI0_CS3_SOD_REG PIOA_SODR 00654 #elif SBBI0_CS3_PORT == NUTGPIO_PORTB 00655 #define SBBI0_CS3_PE_REG PIOB_PER 00656 #define SBBI0_CS3_OE_REG PIOB_OER 00657 #define SBBI0_CS3_COD_REG PIOB_CODR 00658 #define SBBI0_CS3_SOD_REG PIOB_SODR 00659 #elif SBBI0_CS3_PORT == NUTGPIO_PORTC 00660 #define SBBI0_CS3_PE_REG PIOC_PER 00661 #define SBBI0_CS3_OE_REG PIOC_OER 00662 #define SBBI0_CS3_COD_REG PIOC_CODR 00663 #define SBBI0_CS3_SOD_REG PIOC_SODR 00664 #endif 00665 00667 #define SBBI0_CS3_ENA() \ 00668 outr(SBBI0_CS3_PE_REG, _BV(SBBI0_CS3_BIT)); \ 00669 outr(SBBI0_CS3_OE_REG, _BV(SBBI0_CS3_BIT)) 00670 00671 #define SBBI0_CS3_CLR() outr(SBBI0_CS3_COD_REG, _BV(SBBI0_CS3_BIT)) 00672 00673 #define SBBI0_CS3_SET() outr(SBBI0_CS3_SOD_REG, _BV(SBBI0_CS3_BIT)) 00674 00675 #else /* SBBI0_CS3_BIT */ 00676 00677 #define SBBI0_CS3_ENA() 00678 #define SBBI0_CS3_CLR() 00679 #define SBBI0_CS3_SET() 00680 00681 #endif /* SBBI0_CS3_BIT */ 00682 00683 #ifdef SBBI0_RST0_BIT 00684 00685 #ifndef SBBI0_RST0_PORT 00686 #define SBBI0_RST0_PORT NUTGPIO_PORT 00687 #endif 00688 00689 #if SBBI0_RST0_PORT == NUTGPIO_PORT 00690 #define SBBI0_RST0_PE_REG PIO_PER 00691 #define SBBI0_RST0_OE_REG PIO_OER 00692 #define SBBI0_RST0_COD_REG PIO_CODR 00693 #define SBBI0_RST0_SOD_REG PIO_SODR 00694 #elif SBBI0_RST0_PORT == NUTGPIO_PORTA 00695 #define SBBI0_RST0_PE_REG PIOA_PER 00696 #define SBBI0_RST0_OE_REG PIOA_OER 00697 #define SBBI0_RST0_COD_REG PIOA_CODR 00698 #define SBBI0_RST0_SOD_REG PIOA_SODR 00699 #elif SBBI0_RST0_PORT == NUTGPIO_PORTB 00700 #define SBBI0_RST0_PE_REG PIOB_PER 00701 #define SBBI0_RST0_OE_REG PIOB_OER 00702 #define SBBI0_RST0_COD_REG PIOB_CODR 00703 #define SBBI0_RST0_SOD_REG PIOB_SODR 00704 #elif SBBI0_RST0_PORT == NUTGPIO_PORTC 00705 #define SBBI0_RST0_PE_REG PIOC_PER 00706 #define SBBI0_RST0_OE_REG PIOC_OER 00707 #define SBBI0_RST0_COD_REG PIOC_CODR 00708 #define SBBI0_RST0_SOD_REG PIOC_SODR 00709 #endif 00710 00712 #define SBBI0_RST0_ENA() \ 00713 outr(SBBI0_RST0_PE_REG, _BV(SBBI0_RST0_BIT)); \ 00714 outr(SBBI0_RST0_OE_REG, _BV(SBBI0_RST0_BIT)) 00715 00716 #define SBBI0_RST0_CLR() outr(SBBI0_RST0_COD_REG, _BV(SBBI0_RST0_BIT)) 00717 00718 #define SBBI0_RST0_SET() outr(SBBI0_RST0_SOD_REG, _BV(SBBI0_RST0_BIT)) 00719 00720 #else /* SBBI0_RST0_BIT */ 00721 00722 #define SBBI0_RST0_ENA() 00723 #define SBBI0_RST0_CLR() 00724 #define SBBI0_RST0_SET() 00725 00726 #endif /* SBBI0_RST0_BIT */ 00727 00728 #ifdef SBBI0_RST1_BIT 00729 00730 #ifndef SBBI0_RST1_PORT 00731 #define SBBI0_RST1_PORT NUTGPIO_PORT 00732 #endif 00733 00734 #if SBBI0_RST1_PORT == NUTGPIO_PORT 00735 #define SBBI0_RST1_PE_REG PIO_PER 00736 #define SBBI0_RST1_OE_REG PIO_OER 00737 #define SBBI0_RST1_COD_REG PIO_CODR 00738 #define SBBI0_RST1_SOD_REG PIO_SODR 00739 #elif SBBI0_RST1_PORT == NUTGPIO_PORTA 00740 #define SBBI0_RST1_PE_REG PIOA_PER 00741 #define SBBI0_RST1_OE_REG PIOA_OER 00742 #define SBBI0_RST1_COD_REG PIOA_CODR 00743 #define SBBI0_RST1_SOD_REG PIOA_SODR 00744 #elif SBBI0_RST1_PORT == NUTGPIO_PORTB 00745 #define SBBI0_RST1_PE_REG PIOB_PER 00746 #define SBBI0_RST1_OE_REG PIOB_OER 00747 #define SBBI0_RST1_COD_REG PIOB_CODR 00748 #define SBBI0_RST1_SOD_REG PIOB_SODR 00749 #elif SBBI0_RST1_PORT == NUTGPIO_PORTC 00750 #define SBBI0_RST1_PE_REG PIOC_PER 00751 #define SBBI0_RST1_OE_REG PIOC_OER 00752 #define SBBI0_RST1_COD_REG PIOC_CODR 00753 #define SBBI0_RST1_SOD_REG PIOC_SODR 00754 #endif 00755 00757 #define SBBI0_RST1_ENA() \ 00758 outr(SBBI0_RST1_PE_REG, _BV(SBBI0_RST1_BIT)); \ 00759 outr(SBBI0_RST1_OE_REG, _BV(SBBI0_RST1_BIT)) 00760 00761 #define SBBI0_RST1_CLR() outr(SBBI0_RST1_COD_REG, _BV(SBBI0_RST1_BIT)) 00762 00763 #define SBBI0_RST1_SET() outr(SBBI0_RST1_SOD_REG, _BV(SBBI0_RST1_BIT)) 00764 00765 #else /* SBBI0_RST1_BIT */ 00766 00767 #define SBBI0_RST1_ENA() 00768 #define SBBI0_RST1_CLR() 00769 #define SBBI0_RST1_SET() 00770 00771 #endif /* SBBI0_RST1_BIT */ 00772 00773 #ifdef SBBI0_RST2_BIT 00774 00775 #ifndef SBBI0_RST2_PORT 00776 #define SBBI0_RST2_PORT NUTGPIO_PORT 00777 #endif 00778 00779 #if SBBI0_RST2_PORT == NUTGPIO_PORT 00780 #define SBBI0_RST2_PE_REG PIO_PER 00781 #define SBBI0_RST2_OE_REG PIO_OER 00782 #define SBBI0_RST2_COD_REG PIO_CODR 00783 #define SBBI0_RST2_SOD_REG PIO_SODR 00784 #elif SBBI0_RST2_PORT == NUTGPIO_PORTA 00785 #define SBBI0_RST2_PE_REG PIOA_PER 00786 #define SBBI0_RST2_OE_REG PIOA_OER 00787 #define SBBI0_RST2_COD_REG PIOA_CODR 00788 #define SBBI0_RST2_SOD_REG PIOA_SODR 00789 #elif SBBI0_RST2_PORT == NUTGPIO_PORTB 00790 #define SBBI0_RST2_PE_REG PIOB_PER 00791 #define SBBI0_RST2_OE_REG PIOB_OER 00792 #define SBBI0_RST2_COD_REG PIOB_CODR 00793 #define SBBI0_RST2_SOD_REG PIOB_SODR 00794 #elif SBBI0_RST2_PORT == NUTGPIO_PORTC 00795 #define SBBI0_RST2_PE_REG PIOC_PER 00796 #define SBBI0_RST2_OE_REG PIOC_OER 00797 #define SBBI0_RST2_COD_REG PIOC_CODR 00798 #define SBBI0_RST2_SOD_REG PIOC_SODR 00799 #endif 00800 00802 #define SBBI0_RST2_ENA() \ 00803 outr(SBBI0_RST2_PE_REG, _BV(SBBI0_RST2_BIT)); \ 00804 outr(SBBI0_RST2_OE_REG, _BV(SBBI0_RST2_BIT)) 00805 00806 #define SBBI0_RST2_CLR() outr(SBBI0_RST2_COD_REG, _BV(SBBI0_RST2_BIT)) 00807 00808 #define SBBI0_RST2_SET() outr(SBBI0_RST2_SOD_REG, _BV(SBBI0_RST2_BIT)) 00809 00810 #else /* SBBI0_RST2_BIT */ 00811 00812 #define SBBI0_RST2_ENA() 00813 #define SBBI0_RST2_CLR() 00814 #define SBBI0_RST2_SET() 00815 00816 #endif /* SBBI0_RST2_BIT */ 00817 00818 #ifdef SBBI0_RST3_BIT 00819 00820 #ifndef SBBI0_RST3_PORT 00821 #define SBBI0_RST3_PORT NUTGPIO_PORT 00822 #endif 00823 00824 #if SBBI0_RST3_PORT == NUTGPIO_PORT 00825 #define SBBI0_RST3_PE_REG PIO_PER 00826 #define SBBI0_RST3_OE_REG PIO_OER 00827 #define SBBI0_RST3_COD_REG PIO_CODR 00828 #define SBBI0_RST3_SOD_REG PIO_SODR 00829 #elif SBBI0_RST3_PORT == NUTGPIO_PORTA 00830 #define SBBI0_RST3_PE_REG PIOA_PER 00831 #define SBBI0_RST3_OE_REG PIOA_OER 00832 #define SBBI0_RST3_COD_REG PIOA_CODR 00833 #define SBBI0_RST3_SOD_REG PIOA_SODR 00834 #elif SBBI0_RST3_PORT == NUTGPIO_PORTB 00835 #define SBBI0_RST3_PE_REG PIOB_PER 00836 #define SBBI0_RST3_OE_REG PIOB_OER 00837 #define SBBI0_RST3_COD_REG PIOB_CODR 00838 #define SBBI0_RST3_SOD_REG PIOB_SODR 00839 #elif SBBI0_RST3_PORT == NUTGPIO_PORTC 00840 #define SBBI0_RST3_PE_REG PIOC_PER 00841 #define SBBI0_RST3_OE_REG PIOC_OER 00842 #define SBBI0_RST3_COD_REG PIOC_CODR 00843 #define SBBI0_RST3_SOD_REG PIOC_SODR 00844 #endif 00845 00847 #define SBBI0_RST3_ENA() \ 00848 outr(SBBI0_RST3_PE_REG, _BV(SBBI0_RST3_BIT)); \ 00849 outr(SBBI0_RST3_OE_REG, _BV(SBBI0_RST3_BIT)) 00850 00851 #define SBBI0_RST3_CLR() outr(SBBI0_RST3_COD_REG, _BV(SBBI0_RST3_BIT)) 00852 00853 #define SBBI0_RST3_SET() outr(SBBI0_RST3_SOD_REG, _BV(SBBI0_RST3_BIT)) 00854 00855 #else /* SBBI0_RST3_BIT */ 00856 00857 #define SBBI0_RST3_ENA() 00858 #define SBBI0_RST3_CLR() 00859 #define SBBI0_RST3_SET() 00860 00861 #endif /* SBBI0_RST3_BIT */ 00862 00863 #ifdef SBBI0_SCK_BIT 00864 00865 #ifndef SBBI0_SCK_PORT 00866 #define SBBI0_SCK_PORT NUTGPIO_PORT 00867 #endif 00868 00869 #if SBBI0_SCK_PORT == NUTGPIO_PORT 00870 #define SBBI0_SCK_PE_REG PIO_PER 00871 #define SBBI0_SCK_OE_REG PIO_OER 00872 #define SBBI0_SCK_COD_REG PIO_CODR 00873 #define SBBI0_SCK_SOD_REG PIO_SODR 00874 #elif SBBI0_SCK_PORT == NUTGPIO_PORTA 00875 #define SBBI0_SCK_PE_REG PIOA_PER 00876 #define SBBI0_SCK_OE_REG PIOA_OER 00877 #define SBBI0_SCK_COD_REG PIOA_CODR 00878 #define SBBI0_SCK_SOD_REG PIOA_SODR 00879 #elif SBBI0_SCK_PORT == NUTGPIO_PORTB 00880 #define SBBI0_SCK_PE_REG PIOB_PER 00881 #define SBBI0_SCK_OE_REG PIOB_OER 00882 #define SBBI0_SCK_COD_REG PIOB_CODR 00883 #define SBBI0_SCK_SOD_REG PIOB_SODR 00884 #elif SBBI0_SCK_PORT == NUTGPIO_PORTC 00885 #define SBBI0_SCK_PE_REG PIOC_PER 00886 #define SBBI0_SCK_OE_REG PIOC_OER 00887 #define SBBI0_SCK_COD_REG PIOC_CODR 00888 #define SBBI0_SCK_SOD_REG PIOC_SODR 00889 #endif 00890 00892 #define SBBI0_SCK_ENA() \ 00893 outr(SBBI0_SCK_PE_REG, _BV(SBBI0_SCK_BIT)); \ 00894 outr(SBBI0_SCK_OE_REG, _BV(SBBI0_SCK_BIT)) 00895 00896 #define SBBI0_SCK_CLR() outr(SBBI0_SCK_COD_REG, _BV(SBBI0_SCK_BIT)) 00897 00898 #define SBBI0_SCK_SET() outr(SBBI0_SCK_SOD_REG, _BV(SBBI0_SCK_BIT)) 00899 00900 #ifdef SBBI0_MOSI_BIT 00901 00902 #ifndef SBBI0_MOSI_PORT 00903 #define SBBI0_MOSI_PORT NUTGPIO_PORT 00904 #endif 00905 00906 #if SBBI0_MOSI_PORT == NUTGPIO_PORT 00907 #define SBBI0_MOSI_PE_REG PIO_PER 00908 #define SBBI0_MOSI_OE_REG PIO_OER 00909 #define SBBI0_MOSI_COD_REG PIO_CODR 00910 #define SBBI0_MOSI_SOD_REG PIO_SODR 00911 #elif SBBI0_MOSI_PORT == NUTGPIO_PORTA 00912 #define SBBI0_MOSI_PE_REG PIOA_PER 00913 #define SBBI0_MOSI_OE_REG PIOA_OER 00914 #define SBBI0_MOSI_COD_REG PIOA_CODR 00915 #define SBBI0_MOSI_SOD_REG PIOA_SODR 00916 #elif SBBI0_MOSI_PORT == NUTGPIO_PORTB 00917 #define SBBI0_MOSI_PE_REG PIOB_PER 00918 #define SBBI0_MOSI_OE_REG PIOB_OER 00919 #define SBBI0_MOSI_COD_REG PIOB_CODR 00920 #define SBBI0_MOSI_SOD_REG PIOB_SODR 00921 #elif SBBI0_MOSI_PORT == NUTGPIO_PORTC 00922 #define SBBI0_MOSI_PE_REG PIOC_PER 00923 #define SBBI0_MOSI_OE_REG PIOC_OER 00924 #define SBBI0_MOSI_COD_REG PIOC_CODR 00925 #define SBBI0_MOSI_SOD_REG PIOC_SODR 00926 #endif 00927 00929 #define SBBI0_MOSI_ENA() \ 00930 outr(SBBI0_MOSI_PE_REG, _BV(SBBI0_MOSI_BIT)); \ 00931 outr(SBBI0_MOSI_OE_REG, _BV(SBBI0_MOSI_BIT)) 00932 00933 #define SBBI0_MOSI_CLR() outr(SBBI0_MOSI_COD_REG, _BV(SBBI0_MOSI_BIT)) 00934 00935 #define SBBI0_MOSI_SET() outr(SBBI0_MOSI_SOD_REG, _BV(SBBI0_MOSI_BIT)) 00936 00937 #else /* SBBI0_MOSI_BIT */ 00938 00939 #define SBBI0_MOSI_ENA() 00940 #define SBBI0_MOSI_CLR() 00941 #define SBBI0_MOSI_SET() 00942 00943 #endif /* SBBI0_MOSI_BIT */ 00944 00945 #ifdef SBBI0_MISO_BIT 00946 00947 #ifndef SBBI0_MISO_PORT 00948 #define SBBI0_MISO_PORT NUTGPIO_PORT 00949 #endif 00950 00951 #if SBBI0_MISO_PORT == NUTGPIO_PORT 00952 #define SBBI0_MISO_PE_REG PIO_PER 00953 #define SBBI0_MISO_OD_REG PIO_ODR 00954 #define SBBI0_MISO_PDS_REG PIO_PDSR 00955 #elif SBBI0_MISO_PORT == NUTGPIO_PORTA 00956 #define SBBI0_MISO_PE_REG PIOA_PER 00957 #define SBBI0_MISO_OD_REG PIOA_ODR 00958 #define SBBI0_MISO_PDS_REG PIOA_PDSR 00959 #elif SBBI0_MISO_PORT == NUTGPIO_PORTB 00960 #define SBBI0_MISO_PE_REG PIOB_PER 00961 #define SBBI0_MISO_OD_REG PIOB_ODR 00962 #define SBBI0_MISO_PDS_REG PIOB_PDSR 00963 #elif SBBI0_MISO_PORT == NUTGPIO_PORTC 00964 #define SBBI0_MISO_PE_REG PIOC_PER 00965 #define SBBI0_MISO_OD_REG PIOC_ODR 00966 #define SBBI0_MISO_PDS_REG PIOC_PDSR 00967 #endif 00968 00970 #define SBBI0_MISO_ENA() \ 00971 outr(SBBI0_MISO_PE_REG, _BV(SBBI0_MISO_BIT)); \ 00972 outr(SBBI0_MISO_OD_REG, _BV(SBBI0_MISO_BIT)) 00973 00974 #define SBBI0_MISO_TST() ((inr(SBBI0_MISO_PDS_REG) & _BV(SBBI0_MISO_BIT)) == _BV(SBBI0_MISO_BIT)) 00975 00976 #else /* SBBI0_MISO_BIT */ 00977 00978 #define SBBI0_MISO_ENA() 00979 #define SBBI0_MISO_TST() 0 00980 00981 #endif /* SBBI0_MISO_BIT */ 00982 00983 #else /* SBBI0_SCK_BIT */ 00984 00985 #define SBBI0_SCK_ENA() 00986 #define SBBI0_SCK_CLR() 00987 #define SBBI0_SCK_SET() 00988 00989 #define SBBI0_MOSI_ENA() 00990 #define SBBI0_MOSI_CLR() 00991 #define SBBI0_MOSI_SET() 00992 00993 #define SBBI0_MISO_ENA() 00994 #define SBBI0_MISO_TST() 0 00995 00996 #endif /* SBBI0_SCK_BIT */ 00997 00998 #endif /* MCU */ 00999 01000 #define SBBI0_INIT() \ 01001 { \ 01002 SBBI0_SCK_CLR(); \ 01003 SBBI0_SCK_ENA(); \ 01004 SBBI0_MOSI_CLR(); \ 01005 SBBI0_MOSI_ENA(); \ 01006 SBBI0_MISO_ENA(); \ 01007 } 01008 01009 __BEGIN_DECLS 01010 /* Function prototypes */ 01011 01012 extern int Sbbi0SetMode(ureg_t ix, ureg_t mode); 01013 extern void Sbbi0SetSpeed(ureg_t ix, uint32_t rate); 01014 extern void Sbbi0Enable(ureg_t ix); 01015 extern void Sbbi0ChipReset(ureg_t ix, ureg_t hi); 01016 extern void Sbbi0ChipSelect(ureg_t ix, ureg_t hi); 01017 extern void Sbbi0SelectDevice(ureg_t ix); 01018 extern void Sbbi0DeselectDevice(ureg_t ix); 01019 extern void Sbbi0NegSelectDevice(ureg_t ix); 01020 extern void Sbbi0NegDeselectDevice(ureg_t ix); 01021 extern uint8_t Sbbi0Byte(uint8_t data); 01022 extern void Sbbi0Transact(CONST void *wdata, void *rdata, size_t len); 01023 01024 __END_DECLS 01025 /* End of prototypes */ 01026 01027 #endif