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00056 #include <arch/arm.h>
00057 #include <dev/irqreg.h>
00058
00059 #ifndef NUT_IRQPRI_IRQ0
00060 #define NUT_IRQPRI_IRQ0 4
00061 #endif
00062
00063 static int Interrupt0Ctl(int cmd, void *param);
00064
00065 IRQ_HANDLER sig_INTERRUPT0 = {
00066 #ifdef NUT_PERFMON
00067 0,
00068 #endif
00069 NULL,
00070 NULL,
00071 Interrupt0Ctl
00072 };
00073
00077 static void Interrupt0Entry(void) __attribute__ ((naked));
00078 void Interrupt0Entry(void)
00079 {
00080 IRQ_ENTRY();
00081 #ifdef NUT_PERFMON
00082 sig_INTERRUPT0.ir_count++;
00083 #endif
00084 if (sig_INTERRUPT0.ir_handler) {
00085 (sig_INTERRUPT0.ir_handler) (sig_INTERRUPT0.ir_arg);
00086 }
00087 IRQ_EXIT();
00088 }
00089
00105 static int Interrupt0Ctl(int cmd, void *param)
00106 {
00107 int rc = 0;
00108 unsigned int *ival = (unsigned int *)param;
00109 int_fast8_t enabled = inr(AIC_IMR) & _BV(IRQ0_ID);
00110
00111
00112 if (enabled) {
00113 outr(AIC_IDCR, _BV(IRQ0_ID));
00114 }
00115
00116 switch(cmd) {
00117 case NUT_IRQCTL_INIT:
00118
00119 outr(AIC_SVR(IRQ0_ID), (unsigned int)Interrupt0Entry);
00120
00121 outr(AIC_SMR(IRQ0_ID), AIC_SRCTYPE_EXT_NEGATIVE_EDGE | NUT_IRQPRI_IRQ0);
00122
00123 outr(AIC_ICCR, _BV(IRQ0_ID));
00124 break;
00125 case NUT_IRQCTL_STATUS:
00126 if (enabled) {
00127 *ival |= 1;
00128 }
00129 else {
00130 *ival &= ~1;
00131 }
00132 break;
00133 case NUT_IRQCTL_ENABLE:
00134 enabled = 1;
00135 break;
00136 case NUT_IRQCTL_DISABLE:
00137 enabled = 0;
00138 break;
00139 case NUT_IRQCTL_GETMODE:
00140 {
00141 unsigned int val = inr(AIC_SMR(IRQ0_ID)) & AIC_SRCTYPE;
00142 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00143 *ival = NUT_IRQMODE_LOWLEVEL;
00144 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00145 *ival = NUT_IRQMODE_HIGHLEVEL;
00146 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00147 *ival = NUT_IRQMODE_RISINGEDGE;
00148 } else {
00149 *ival = NUT_IRQMODE_FALLINGEDGE;
00150 }
00151 }
00152 break;
00153 case NUT_IRQCTL_SETMODE:
00154 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00155 outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00156 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00157 outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00158 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00159 outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00160 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00161 outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00162 } else {
00163 rc = -1;
00164 }
00165 break;
00166 case NUT_IRQCTL_GETPRIO:
00167 *ival = inr(AIC_SMR(IRQ0_ID)) & AIC_PRIOR;
00168 break;
00169 case NUT_IRQCTL_SETPRIO:
00170 outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_PRIOR) | *ival);
00171 break;
00172 #ifdef NUT_PERFMON
00173 case NUT_IRQCTL_GETCOUNT:
00174 *ival = (unsigned int)sig_INTERRUPT0.ir_count;
00175 sig_INTERRUPT0.ir_count = 0;
00176 break;
00177 #endif
00178 default:
00179 rc = -1;
00180 break;
00181 }
00182
00183
00184 if (enabled) {
00185 outr(AIC_IECR, _BV(IRQ0_ID));
00186 #if defined(PMC_PCER)
00187 outr(PMC_PCER, _BV(IRQ0_ID));
00188 #endif
00189 }
00190 return rc;
00191 }
00192