at91_aic.h

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#ifndef _ARCH_ARM_AT91_AIC_H_
#define _ARCH_ARM_AT91_AIC_H_

/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */


#define AIC_SMR(i)  (AIC_BASE + i * 4)

#define AIC_PRIOR                       0x00000007

#define AIC_SRCTYPE                     0x00000060

#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000      
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x00000020      
#define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00000000      
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020      
#define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x00000040      
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060      


#define AIC_SVR(i)  (AIC_BASE + 0x80 + i * 4)

#define AIC_IVR_OFF                 0x00000100  
#define AIC_IVR     (AIC_BASE + AIC_IVR_OFF)    


#define AIC_FVR_OFF                 0x00000104  
#define AIC_FVR     (AIC_BASE + AIC_FVR_OFF)    


#define AIC_ISR_OFF                 0x00000108  
#define AIC_ISR     (AIC_BASE + AIC_ISR_OFF)    
#define AIC_IRQID                   0x0000001F  


#define AIC_IPR_OFF                 0x0000010C  
#define AIC_IPR     (AIC_BASE + AIC_IPR_OFF)    


#define AIC_IMR_OFF                 0x00000110  
#define AIC_IMR     (AIC_BASE + AIC_IMR_OFF)    


#define AIC_CISR_OFF                0x00000114  
#define AIC_CISR    (AIC_BASE + AIC_CISR_OFF)   
#define AIC_NFIQ                    0x00000001  
#define AIC_NIRQ                    0x00000002  


#define AIC_IECR_OFF                0x00000120  
#define AIC_IECR    (AIC_BASE + AIC_IECR_OFF)   


#define AIC_IDCR_OFF                0x00000124  
#define AIC_IDCR    (AIC_BASE + AIC_IDCR_OFF)   


#define AIC_ICCR_OFF                0x00000128  
#define AIC_ICCR    (AIC_BASE + AIC_ICCR_OFF)   


#define AIC_ISCR_OFF                0x0000012C  
#define AIC_ISCR    (AIC_BASE + AIC_ISCR_OFF)   


#define AIC_EOICR_OFF               0x00000130  
#define AIC_EOICR   (AIC_BASE + AIC_EOICR_OFF)  


#define AIC_SPU_OFF                 0x00000134  
#define AIC_SPU     (AIC_BASE + AIC_SPU_OFF)    


#define AIC_DCR_OFF                 0x0000138   
#define AIC_DCR     (AIC_BASE + AIC_DCR_OFF)    


#define AIC_FFER_OFF                0x00000140  
#define AIC_FFER    (AIC_BASE + AIC_FFER_OFF)   


#define AIC_FFDR_OFF                0x00000144  
#define AIC_FFDR    (AIC_BASE + AIC_FFDR_OFF)   


#define AIC_FFSR_OFF                0x00000148  
#define AIC_FFSR    (AIC_BASE + AIC_FFSR_OFF)   


#endif                          /* _ARCH_ARM_AT91_AIC_H_ */