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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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00001 #ifndef _ARCH_ARM_AT91_SPI_H_ 00002 #define _ARCH_ARM_AT91_SPI_H_ 00003 00004 /* 00005 * Copyright (C) 00006 */ 00007 00040 00043 #define SPI_CR_OFF 0x00000000 00045 #define SPI_SPIEN 0x00000001 00046 #define SPI_SPIDIS 0x00000002 00047 #define SPI_SWRST 0x00000080 00048 #define SPI_LASTXFER 0x01000000 00050 00051 00053 #define SPI_MR_OFF 0x00000004 00055 #define SPI_MSTR 0x00000001 00056 #define SPI_PS 0x00000002 00057 #define SPI_PCSDEC 0x00000004 00058 #define SPI_FDIV 0x00000008 00059 #define SPI_MODFDIS 0x00000010 00060 #define SPI_LLB 0x00000080 00061 #define SPI_PCS 0x000F0000 00062 #define SPI_PCS_0 0x000E0000 00063 #define SPI_PCS_1 0x000D0000 00064 #define SPI_PCS_2 0x000B0000 00065 #define SPI_PCS_3 0x00070000 00066 #define SPI_PCS_LSB 16 00067 #define SPI_DLYBCS 0xFF000000 00068 #define SPI_DLYBCS_LSB 24 00070 00071 00073 #define SPI_RDR_OFF 0x00000008 00075 #define SPI_RD 0x0000FFFF 00076 #define SPI_RD_LSB 0 00078 00079 00081 #define SPI_TDR_OFF 0x0000000C 00083 #define SPI_TD 0x0000FFFF 00084 #define SPI_TD_LSB 0 00086 00087 00089 #define SPI_SR_OFF 0x00000010 00090 #define SPI_IER_OFF 0x00000014 00091 #define SPI_IDR_OFF 0x00000018 00092 #define SPI_IMR_OFF 0x0000001C 00094 #define SPI_RDRF 0x00000001 00095 #define SPI_TDRE 0x00000002 00096 #define SPI_MODF 0x00000004 00097 #define SPI_OVRES 0x00000008 00098 #define SPI_ENDRX 0x00000010 00099 #define SPI_ENDTX 0x00000020 00100 #define SPI_RXBUFF 0x00000040 00101 #define SPI_TXBUFE 0x00000080 00102 #define SPI_NSSR 0x00000100 00103 #define SPI_TXEMPTY 0x00000200 00104 #define SPI_SPIENS 0x00010000 00106 00107 00109 #define SPI_CSR0_OFF 0x00000030 00110 #define SPI_CSR1_OFF 0x00000034 00111 #define SPI_CSR2_OFF 0x00000038 00112 #define SPI_CSR3_OFF 0x0000003C 00114 #define SPI_CPOL 0x00000001 00115 #define SPI_NCPHA 0x00000002 00116 #define SPI_CSAAT 0x00000008 00117 #define SPI_BITS 0x000000F0 00118 #define SPI_BITS_8 0x00000000 00119 #define SPI_BITS_9 0x00000010 00120 #define SPI_BITS_10 0x00000020 00121 #define SPI_BITS_11 0x00000030 00122 #define SPI_BITS_12 0x00000040 00123 #define SPI_BITS_13 0x00000050 00124 #define SPI_BITS_14 0x00000060 00125 #define SPI_BITS_15 0x00000070 00126 #define SPI_BITS_16 0x00000080 00127 #define SPI_BITS_LSB 4 00128 #define SPI_SCBR 0x0000FF00 00129 #define SPI_SCBR_LSB 8 00130 #define SPI_DLYBS 0x00FF0000 00131 #define SPI_DLYBS_LSB 16 00132 #define SPI_DLYBCT 0xFF000000 00133 #define SPI_DLYBCT_LSB 24 00135 00136 00138 #if defined(SPI_BASE) 00139 #define SPI0_BASE SPI_BASE 00140 #define SPI_CR SPI0_CR 00141 #define SPI_MR SPI0_MR 00142 #define SPI_RDR SPI0_RDR 00143 #define SPI_TDR SPI0_TDR 00144 #define SPI_SR SPI0_SR 00145 #define SPI_IER SPI0_IER 00146 #define SPI_IDR SPI0_IDR 00147 #define SPI_IMR SPI0_IMR 00148 #define SPI_CSR0 SPI0_CSR0 00149 #define SPI_CSR1 SPI0_CSR1 00150 #define SPI_CSR2 SPI0_CSR2 00151 #define SPI_CSR3 SPI0_CSR3 00152 #if defined(SPI_HAS_PDC) 00153 #define SPI_RPR SPI0_RPR 00154 #define SPI_RCR SPI0_RCR 00155 #define SPI_TPR SPI0_TPR 00156 #define SPI_TCR SPI0_TCR 00157 #define SPI_RNPR SPI0_RNPR 00158 #define SPI_RNCR SPI0_RNCR 00159 #define SPI_TNPR SPI0_TNPR 00160 #define SPI_TNCR SPI0_TNCR 00161 #define SPI_PTCR SPI0_PTCR 00162 #define SPI_PTSR SPI0_PTSR 00163 #endif /* SPI_HAS_PDC */ 00164 #endif /* SPI_BASE */ 00165 00169 #if defined(SPI0_BASE) 00170 #define SPI0_CR (SPI0_BASE + SPI_CR_OFF) 00171 #define SPI0_MR (SPI0_BASE + SPI_MR_OFF) 00172 #define SPI0_RDR (SPI0_BASE + SPI_RDR_OFF) 00173 #define SPI0_TDR (SPI0_BASE + SPI_TDR_OFF) 00174 #define SPI0_SR (SPI0_BASE + SPI_SR_OFF) 00175 #define SPI0_IER (SPI0_BASE + SPI_IER_OFF) 00176 #define SPI0_IDR (SPI0_BASE + SPI_IDR_OFF) 00177 #define SPI0_IMR (SPI0_BASE + SPI_IMR_OFF) 00178 #define SPI0_CSR0 (SPI0_BASE + SPI_CSR0_OFF) 00179 #define SPI0_CSR1 (SPI0_BASE + SPI_CSR1_OFF) 00180 #define SPI0_CSR2 (SPI0_BASE + SPI_CSR2_OFF) 00181 #define SPI0_CSR3 (SPI0_BASE + SPI_CSR3_OFF) 00182 #if defined(SPI_HAS_PDC) 00183 #define SPI0_RPR (SPI0_BASE + PERIPH_RPR_OFF) 00184 #define SPI0_RCR (SPI0_BASE + PERIPH_RCR_OFF) 00185 #define SPI0_TPR (SPI0_BASE + PERIPH_TPR_OFF) 00186 #define SPI0_TCR (SPI0_BASE + PERIPH_TCR_OFF) 00187 #define SPI0_RNPR (SPI0_BASE + PERIPH_RNPR_OFF) 00188 #define SPI0_RNCR (SPI0_BASE + PERIPH_RNCR_OFF) 00189 #define SPI0_TNPR (SPI0_BASE + PERIPH_TNPR_OFF) 00190 #define SPI0_TNCR (SPI0_BASE + PERIPH_TNCR_OFF) 00191 #define SPI0_PTCR (SPI0_BASE + PERIPH_PTCR_OFF) 00192 #define SPI0_PTSR (SPI0_BASE + PERIPH_PTSR_OFF) 00193 #endif /* SPI_HAS_PDC */ 00194 #endif /* SPI0_BASE */ 00195 00199 #if defined(SPI1_BASE) 00200 #define SPI1_CR (SPI1_BASE + SPI_CR_OFF) 00201 #define SPI1_MR (SPI1_BASE + SPI_MR_OFF) 00202 #define SPI1_RDR (SPI1_BASE + SPI_RDR_OFF) 00203 #define SPI1_TDR (SPI1_BASE + SPI_TDR_OFF) 00204 #define SPI1_SR (SPI1_BASE + SPI_SR_OFF) 00205 #define SPI1_IER (SPI1_BASE + SPI_IER_OFF) 00206 #define SPI1_IDR (SPI1_BASE + SPI_IDR_OFF) 00207 #define SPI1_IMR (SPI1_BASE + SPI_IMR_OFF) 00208 #define SPI1_CSR0 (SPI1_BASE + SPI_CSR0_OFF) 00209 #define SPI1_CSR1 (SPI1_BASE + SPI_CSR1_OFF) 00210 #define SPI1_CSR2 (SPI1_BASE + SPI_CSR2_OFF) 00211 #define SPI1_CSR3 (SPI1_BASE + SPI_CSR3_OFF) 00212 #if defined(SPI_HAS_PDC) 00213 #define SPI1_RPR (SPI1_BASE + PERIPH_RPR_OFF) 00214 #define SPI1_RCR (SPI1_BASE + PERIPH_RCR_OFF) 00215 #define SPI1_TPR (SPI1_BASE + PERIPH_TPR_OFF) 00216 #define SPI1_TCR (SPI1_BASE + PERIPH_TCR_OFF) 00217 #define SPI1_RNPR (SPI1_BASE + PERIPH_RNPR_OFF) 00218 #define SPI1_RNCR (SPI1_BASE + PERIPH_RNCR_OFF) 00219 #define SPI1_TNPR (SPI1_BASE + PERIPH_TNPR_OFF) 00220 #define SPI1_TNCR (SPI1_BASE + PERIPH_TNCR_OFF) 00221 #define SPI1_PTCR (SPI1_BASE + PERIPH_PTCR_OFF) 00222 #define SPI1_PTSR (SPI1_BASE + PERIPH_PTSR_OFF) 00223 #endif /* SPI_HAS_PDC */ 00224 #endif /* SPI1_BASE */ 00225 00227 00229 #endif /* _ARCH_ARM_AT91_SPI_H_ */