at91_mci.h

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#ifndef _ARCH_ARM_AT91_MCI_H_
#define _ARCH_ARM_AT91_MCI_H_

/*
 * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */


#define MCI_CR_OFF              0x00000000      
#define MCI_CR      (MCI_BASE + MCI_CR_OFF)     
#define MCI_MCIEN               0x00000001      
#define MCI_MCIDIS              0x00000002      
#define MCI_PWSEN               0x00000004      
#define MCI_PWSDIS              0x00000008      
#define MCI_SWRST               0x00000080      


#define MCI_MR_OFF              0x00000004      
#define MCI_MR      (MCI_BASE + MCI_MR_OFF)     
#define MCI_CLKDIV              0x000000FF      
#define MCI_CLKDIV_LSB                  0       
#define MCI_PWSDIV              0x00000700      
#define MCI_PWSDIV_LSB                  8       
#define MCI_RDPROOF             0x00000800      
#define MCI_WRPROOF             0x00001000      
#define MCI_PDCFBYTE            0x00002000      
#define MCI_PDCPADV             0x00004000      
#define MCI_PDCMODE             0x00008000      
#define MCI_BLKLEN              0xFFFF0000      
#define MCI_BLKLEN_LSB                  16      


#define MCI_DTOR_OFF            0x00000008      
#define MCI_DTOR    (MCI_BASE + MCI_DTOR_OFF)   
#define MCI_DTOCYC              0x0000000F      
#define MCI_DTOCYC_LSB                  0       
#define MCI_DTOMUL              0x00000070      
#define MCI_DTOMUL_1            0x00000000      
#define MCI_DTOMUL_16           0x00000010      
#define MCI_DTOMUL_128          0x00000020      
#define MCI_DTOMUL_256          0x00000030      
#define MCI_DTOMUL_1K           0x00000040      
#define MCI_DTOMUL_4K           0x00000050      
#define MCI_DTOMUL_64K          0x00000060      
#define MCI_DTOMUL_1M           0x00000070      


#define MCI_SDCR_OFF            0x0000000C      
#define MCI_SDCR    (MCI_BASE + MCI_SDCR_OFF)   
#define MCI_SDCSEL              0x00000003      
#define MCI_SDCSEL_SLOTA        0x00000000      
#define MCI_SDCSEL_SLOTB        0x00000001      
#define MCI_SDCBUS              0x00000080      


#define MCI_ARGR_OFF            0x00000010      
#define MCI_ARGR    (MCI_BASE + MCI_ARGR_OFF)   


#define MCI_CMDR_OFF            0x00000014      
#define MCI_CMDR    (MCI_BASE + MCI_CMDR_OFF)   
#define MCI_CMDNB               0x0000003F      
#define MCI_CMDNB_LSB                   0       
#define MCI_RSPTYP              0x000000C0      
#define MCI_RSPTYP_NONE         0x00000000      
#define MCI_RSPTYP_48           0x00000040      
#define MCI_RSPTYP_136          0x00000080      
#define MCI_SPCMD               0x00000700      
#define MCI_SPCMD_NONE          0x00000000      
#define MCI_SPCMD_INIT          0x00000100      
#define MCI_SPCMD_SYNC          0x00000200      
#define MCI_SPCMD_ICMD          0x00000400      
#define MCI_SPCMD_IRSP          0x00000500      
#define MCI_OPDCMD              0x00000800      
#define MCI_OPCMD               MCI_OPDCMD      
#define MCI_MAXLAT              0x00001000      
#define MCI_TRCMD               0x00030000      
#define MCI_TRCMD_NONE          0x00000000      
#define MCI_TRCMD_START         0x00010000      
#define MCI_TRCMD_STOP          0x00020000      
#define MCI_TRDIR               0x00040000      
#define MCI_TRTYP               0x00380000      
#define MCI_TRTYP_MMC_SBLK      0x00000000      
#define MCI_TRTYP_MMC_MBLK      0x00080000      
#define MCI_TRTYP_MMC_STREAM    0x00100000      
#define MCI_TRTYP_SDIO_BYTE     0x00200000      
#define MCI_TRTYP_SDIO_BLK      0x00280000      
#define MCI_IOSPCMD             0x03000000      
#define MCI_IOSPCMD_NONE        0x00000000      
#define MCI_IOSPCMD_SUSPEND     0x01000000      
#define MCI_IOSPCMD_RESUME      0x02000000      


#define MCI_BLKR_OFF            0x00000018      
#define MCI_BLKR    (MCI_BASE + MCI_BLKR_OFF)   
#define MCI_BCNT                0x0000FFFF      
#define MCI_BCNT_LSB                    0       


#define MCI_RSPR_OFF            0x00000020      
#define MCI_RSPR    (MCI_BASE + MCI_RSPR_OFF)   


#define MCI_RDR_OFF             0x00000030      
#define MCI_RDR     (MCI_BASE + MCI_RDR_OFF)    


#define MCI_TDR_OFF             0x00000034      
#define MCI_TDR     (MCI_BASE + MCI_TDR_OFF)    


#define MCI_SR_OFF              0x00000040      
#define MCI_SR      (MCI_BASE + MCI_SR_OFF)     
#define MCI_IER_OFF             0x00000044      
#define MCI_IER     (MCI_BASE + MCI_IER_OFF)    
#define MCI_IDR_OFF             0x00000048      
#define MCI_IDR     (MCI_BASE + MCI_IDR_OFF)    
#define MCI_IMR_OFF             0x0000004C      
#define MCI_IMR     (MCI_BASE + MCI_IMR_OFF)    
#define MCI_CMDRDY              0x00000001      
#define MCI_RXRDY               0x00000002      
#define MCI_TXRDY               0x00000004      
#define MCI_BLKE                0x00000008      
#define MCI_DTIP                0x00000010      
#define MCI_NOTBUSY             0x00000020      
#define MCI_ENDRX               0x00000040      
#define MCI_ENDTX               0x00000080      
#define MCI_SDIOIRQA            0x00000100      
#define MCI_SDIOIRQB            0x00000200      
#define MCI_RXBUFF              0x00004000      
#define MCI_TXBUFE              0x00008000      
#define MCI_RINDE               0x00010000      
#define MCI_RDIRE               0x00020000      
#define MCI_RCRCE               0x00040000      
#define MCI_RENDE               0x00080000      
#define MCI_RTOE                0x00100000      
#define MCI_DCRCE               0x00200000      
#define MCI_DTOE                0x00400000      
#define MCI_OVRE                0x40000000      
#define MCI_UNRE                0x80000000      

#if defined(MCI_HAS_PDC)

#define MCI_RPR    (MCI_BASE + PERIPH_RPR_OFF)  


#define MCI_RCR    (MCI_BASE + PERIPH_RCR_OFF)  


#define MCI_TPR    (MCI_BASE + PERIPH_TPR_OFF)  


#define MCI_TCR    (MCI_BASE + PERIPH_TCR_OFF)  


#define MCI_RNPR   (MCI_BASE + PERIPH_RNPR_OFF) 


#define MCI_RNCR   (MCI_BASE + PERIPH_RNCR_OFF) 


#define MCI_TNPR   (MCI_BASE + PERIPH_TNPR_OFF) 


#define MCI_TNCR   (MCI_BASE + PERIPH_TNCR_OFF) 


#define MCI_PTCR   (MCI_BASE + PERIPH_PTCR_OFF) 


#define MCI_PTSR   (MCI_BASE + PERIPH_PTSR_OFF) 

#endif

#endif                          /* _ARCH_ARM_AT91_MCI_H_ */