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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 #ifndef _LPC17XX_GPDMA_H_ 00002 #define _LPC17XX_GPDMA_H_ 00003 00004 /* 00005 * Copyright (C) 2012 by Ole Reinhardt (ole.reinhardt@embedded-it.de) 00006 * 00007 * All rights reserved. 00008 * 00009 * Redistribution and use in source and binary forms, with or without 00010 * modification, are permitted provided that the following conditions 00011 * are met: 00012 * 00013 * 1. Redistributions of source code must retain the above copyright 00014 * notice, this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright 00016 * notice, this list of conditions and the following disclaimer in the 00017 * documentation and/or other materials provided with the distribution. 00018 * 3. Neither the name of the copyright holders nor the names of 00019 * contributors may be used to endorse or promote products derived 00020 * from this software without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00023 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00024 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00025 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 00026 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00027 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00028 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00029 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00030 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00031 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00032 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00033 * SUCH DAMAGE. 00034 * 00035 * For additional information see http://www.ethernut.de/ 00036 * 00037 * 00038 * Parts taken from lpc177x_8x_gpdma.h 2011-06-02 00039 * 00040 * file lpc177x_8x_gpdma.h 00041 * brief Contains all macro definitions and function prototypes 00042 * support for GPDMA firmware library on LPC177x_8x 00043 * version 1.0 00044 * date 02. June. 2011 00045 * author NXP MCU SW Application Team 00046 * 00047 * Copyright(C) 2011, NXP Semiconductor 00048 * All rights reserved. 00049 * 00050 *********************************************************************** 00051 * Software that is described herein is for illustrative purposes only 00052 * which provides customers with programming information regarding the 00053 * products. This software is supplied "AS IS" without any warranties. 00054 * NXP Semiconductors assumes no responsibility or liability for the 00055 * use of the software, conveys no license or title under any patent, 00056 * copyright, or mask work right to the product. NXP Semiconductors 00057 * reserves the right to make changes in the software without 00058 * notification. NXP Semiconductors also make no representation or 00059 * warranty that such application will be suitable for the specified 00060 * use without further testing or modification. 00061 * Permission to use, copy, modify, and distribute this software and its 00062 * documentation is hereby granted, under NXP Semiconductors' 00063 * relevant copyright in the software, without fee, provided that it 00064 * is used in conjunction with NXP Semiconductors microcontrollers. This 00065 * copyright, permission, and disclaimer notice must appear in all copies of 00066 * this code. 00067 **********************************************************************/ 00068 00075 /*============================================================================* 00076 Public definitions 00077 *============================================================================*/ 00078 00079 /*----------------------------------------------------------------------------* 00080 DMA Connection number definitions 00081 *----------------------------------------------------------------------------*/ 00082 00083 #define GPDMA_CONN_MCI 1 /* SD card */ 00084 #define GPDMA_CONN_SSP0_Tx 2 /* SSP0 Tx */ 00085 #define GPDMA_CONN_SSP0_Rx 3 /* SSP0 Rx */ 00086 #define GPDMA_CONN_SSP1_Tx 4 /* SSP1 Tx */ 00087 #define GPDMA_CONN_SSP1_Rx 5 /* SSP1 Rx */ 00088 #define GPDMA_CONN_SSP2_Tx 6 /* SSP2 Tx */ 00089 #define GPDMA_CONN_SSP2_Rx 7 /* SSP2 Rx */ 00090 #define GPDMA_CONN_ADC 8 /* ADC */ 00091 #define GPDMA_CONN_DAC 9 /* DAC */ 00092 #define GPDMA_CONN_UART0_Tx 10 /* UART0 Tx */ 00093 #define GPDMA_CONN_UART0_Rx 11 /* UART0 Rx */ 00094 #define GPDMA_CONN_UART1_Tx 12 /* UART1 Tx */ 00095 #define GPDMA_CONN_UART1_Rx 13 /* UART1 Rx */ 00096 #define GPDMA_CONN_UART2_Tx 14 /* UART2 Tx */ 00097 #define GPDMA_CONN_UART2_Rx 15 /* UART2 Rx */ 00098 #define GPDMA_CONN_MAT0_0 16 /* MAT0.0 */ 00099 #define GPDMA_CONN_MAT0_1 17 /* MAT0.1 */ 00100 #define GPDMA_CONN_MAT1_0 18 /* MAT1.0 */ 00101 #define GPDMA_CONN_MAT1_1 19 /* MAT1.1 */ 00102 #define GPDMA_CONN_MAT2_0 20 /* MAT2.0 */ 00103 #define GPDMA_CONN_MAT2_1 21 /* MAT2.1 */ 00104 #define GPDMA_CONN_I2S_Channel_0 22 /* I2S channel 0 */ 00105 #define GPDMA_CONN_I2S_Channel_1 23 /* I2S channel 1 */ 00106 #define GPDMA_CONN_UART3_Tx 26 /* UART3 Tx */ 00107 #define GPDMA_CONN_UART3_Rx 27 /* UART3 Rx */ 00108 #define GPDMA_CONN_UART4_Tx 28 /* UART3 Tx */ 00109 #define GPDMA_CONN_UART4_Rx 29 /* UART3 Rx */ 00110 #define GPDMA_CONN_MAT3_0 30 /* MAT3.0 */ 00111 #define GPDMA_CONN_MAT3_1 31 /* MAT3.1 */ 00112 00113 00114 /*----------------------------------------------------------------------------* 00115 GPDMA Transfer type definitions 00116 *----------------------------------------------------------------------------*/ 00117 00118 #define GPDMA_TRANSFERTYPE_M2M 0 /* Memory to memory - DMA control */ 00119 #define GPDMA_TRANSFERTYPE_M2P 1 /* Memory to peripheral - DMA control */ 00120 #define GPDMA_TRANSFERTYPE_P2M 2 /* Peripheral to memory - DMA control */ 00121 #define GPDMA_TRANSFERTYPE_P2P 3 /* Source peripheral to destination peripheral - DMA control */ 00122 #define GPDMA_TRANSFERTYPE_M2P_DEST_CTRL 5 /* Memory to peripheral - Destination peripheral control */ 00123 #define GPDMA_TRANSFERTYPE_P2M_SRC_CTRL 6 /* Peripheral to memory - Source peripheral control */ 00124 00125 00126 /*----------------------------------------------------------------------------* 00127 Burst size in Source and Destination definitions 00128 *----------------------------------------------------------------------------*/ 00129 00130 #define GPDMA_BSIZE_1 0 /* Burst size = 1 */ 00131 #define GPDMA_BSIZE_4 1 /* Burst size = 4 */ 00132 #define GPDMA_BSIZE_8 2 /* Burst size = 8 */ 00133 #define GPDMA_BSIZE_16 3 /* Burst size = 16 */ 00134 #define GPDMA_BSIZE_32 4 /* Burst size = 32 */ 00135 #define GPDMA_BSIZE_64 5 /* Burst size = 64 */ 00136 #define GPDMA_BSIZE_128 6 /* Burst size = 128 */ 00137 #define GPDMA_BSIZE_256 7 /* Burst size = 256 */ 00138 00139 00140 /*----------------------------------------------------------------------------* 00141 Width in Source transfer width and Destination transfer width definitions 00142 *----------------------------------------------------------------------------*/ 00143 00144 #define GPDMA_WIDTH_BYTE 0 /* Width = 1 byte */ 00145 #define GPDMA_WIDTH_HALFWORD 1 /* Width = 2 bytes */ 00146 #define GPDMA_WIDTH_WORD 2 /* Width = 4 bytes */ 00147 00148 00149 /*----------------------------------------------------------------------------* 00150 DMA Request Select Mode definitions 00151 *----------------------------------------------------------------------------*/ 00152 00153 #define GPDMA_REQSEL_UART 0 /* UART TX/RX is selected */ 00154 #define GPDMA_REQSEL_TIMER 1 /* Timer match is selected */ 00155 00156 00157 00158 00159 /*============================================================================* 00160 Bit definitions 00161 *============================================================================*/ 00162 00163 /*----------------------------------------------------------------------------* 00164 Macro defines for DMA Interrupt Status register 00165 *----------------------------------------------------------------------------*/ 00166 00167 #define GPDMA_DMACIntStat_Ch(n) ((1UL << n) & 0xFF) 00168 #define GPDMA_DMACIntStat_BITMASK 0xFF 00169 00170 00171 /*----------------------------------------------------------------------------* 00172 Macro defines for DMA Interrupt Terminal Count Request Status register 00173 *----------------------------------------------------------------------------*/ 00174 00175 #define GPDMA_DMACIntTCStat_Ch(n) ((1UL << n) & 0xFF) 00176 #define GPDMA_DMACIntTCStat_BITMASK 0xFF 00177 00178 00179 /*----------------------------------------------------------------------------* 00180 Macro defines for DMA Interrupt Terminal Count Request Clear register 00181 *----------------------------------------------------------------------------*/ 00182 00183 #define GPDMA_DMACIntTCClear_Ch(n) ((1UL << n) & 0xFF) 00184 #define GPDMA_DMACIntTCClear_BITMASK 0xFF 00185 00186 00187 /*----------------------------------------------------------------------------* 00188 Macro defines for DMA Interrupt Error Status register 00189 *----------------------------------------------------------------------------*/ 00190 00191 #define GPDMA_DMACIntErrStat_Ch(n) ((1UL << n) & 0xFF) 00192 #define GPDMA_DMACIntErrStat_BITMASK 0xFF 00193 00194 00195 /*----------------------------------------------------------------------------* 00196 Macro defines for DMA Interrupt Error Clear register 00197 *----------------------------------------------------------------------------*/ 00198 00199 #define GPDMA_DMACIntErrClr_Ch(n) ((1UL << n) & 0xFF) 00200 #define GPDMA_DMACIntErrClr_BITMASK 0xFF 00201 00202 00203 /*----------------------------------------------------------------------------* 00204 Macro defines for DMA Raw Interrupt Terminal Count Status register 00205 *----------------------------------------------------------------------------*/ 00206 00207 #define GPDMA_DMACRawIntTCStat_Ch(n) ((1UL << n) & 0xFF) 00208 #define GPDMA_DMACRawIntTCStat_BITMASK 0xFF 00209 00210 00211 /*----------------------------------------------------------------------------* 00212 Macro defines for DMA Raw Error Interrupt Status register 00213 *----------------------------------------------------------------------------*/ 00214 00215 #define GPDMA_DMACRawIntErrStat_Ch(n) ((1UL << n) & 0xFF) 00216 #define GPDMA_DMACRawIntErrStat_BITMASK 0xFF 00217 00218 00219 /*----------------------------------------------------------------------------* 00220 Macro defines for DMA Enabled Channel register 00221 *----------------------------------------------------------------------------*/ 00222 00223 #define GPDMA_DMACEnbldChns_Ch(n) ((1UL << n) & 0xFF) 00224 #define GPDMA_DMACEnbldChns_BITMASK 0xFF 00225 00226 00227 /*----------------------------------------------------------------------------* 00228 Macro defines for DMA Software Burst Request register 00229 *----------------------------------------------------------------------------*/ 00230 00231 #define GPDMA_DMACSoftBReq_Src(n) ((1UL << n) & 0xFFFF) 00232 #define GPDMA_DMACSoftBReq_BITMASK 0xFFFF 00233 00234 00235 /*----------------------------------------------------------------------------* 00236 Macro defines for DMA Software Single Request register 00237 *----------------------------------------------------------------------------*/ 00238 00239 #define GPDMA_DMACSoftSReq_Src(n) ((1UL << n) & 0xFFFF) 00240 #define GPDMA_DMACSoftSReq_BITMASK 0xFFFF 00241 00242 00243 /*----------------------------------------------------------------------------* 00244 Macro defines for DMA Software Last Burst Request register 00245 *----------------------------------------------------------------------------*/ 00246 00247 #define GPDMA_DMACSoftLBReq_Src(n) ((1UL << n) & 0xFFFF) 00248 #define GPDMA_DMACSoftLBReq_BITMASK 0xFFFF 00249 00250 00251 /*----------------------------------------------------------------------------* 00252 Macro defines for DMA Software Last Single Request register 00253 *----------------------------------------------------------------------------*/ 00254 00255 #define GPDMA_DMACSoftLSReq_Src(n) ((1UL << n) & 0xFFFF) 00256 #define GPDMA_DMACSoftLSReq_BITMASK 0xFFFF 00257 00258 00259 /*----------------------------------------------------------------------------* 00260 Macro defines for DMA Configuration register 00261 *----------------------------------------------------------------------------*/ 00262 00263 #define GPDMA_DMACConfig_E 0x01 /* DMA Controller enable*/ 00264 #define GPDMA_DMACConfig_M 0x02 /* AHB Master endianness configuration*/ 00265 #define GPDMA_DMACConfig_BITMASK 0x03 00266 00267 00268 /*----------------------------------------------------------------------------* 00269 Macro defines for DMA Synchronization register 00270 *----------------------------------------------------------------------------*/ 00271 00272 #define GPDMA_DMACSync_Src(n) ((1UL << n) & 0xFFFF) 00273 #define GPDMA_DMACSync_BITMASK 0xFFFF 00274 00275 00276 /*----------------------------------------------------------------------------* 00277 Macro defines for DMA Request Select register 00278 *----------------------------------------------------------------------------*/ 00279 00280 #define GPDMA_DMAReqSel_Input(n) ((1UL << (n - 8)) & 0xFF) 00281 #define GPDMA_DMAReqSel_BITMASK 0xFF 00282 00283 00284 /*----------------------------------------------------------------------------* 00285 Macro defines for DMA Channel Linker List Item registers 00286 *----------------------------------------------------------------------------*/ 00287 00288 #define GPDMA_DMACCxLLI_BITMASK 0xFFFFFFFC /* DMA Channel Linker List Item registers bit mask */ 00289 00290 00291 /*----------------------------------------------------------------------------* 00292 Macro defines for DMA channel control registers 00293 *----------------------------------------------------------------------------*/ 00294 00295 #define GPDMA_DMACCxControl_TransferSize(n) ((n & 0xFFF) << 0) /* Transfer size*/ 00296 #define GPDMA_DMACCxControl_SBSize(n) ((n & 0x07) << 12) /* Source burst size */ 00297 #define GPDMA_DMACCxControl_DBSize(n) ((n & 0x07) << 15) /* Destination burst size */ 00298 #define GPDMA_DMACCxControl_SWidth(n) ((n & 0x07) << 18) /* Source transfer width */ 00299 #define GPDMA_DMACCxControl_DWidth(n) ((n & 0x07) << 21) /* Destination transfer width */ 00300 #define GPDMA_DMACCxControl_SI (1UL << 26) /* Source increment */ 00301 #define GPDMA_DMACCxControl_DI (1UL << 27) /* Destination increment */ 00302 #define GPDMA_DMACCxControl_Prot1 (1UL << 28) /* Indicates that the access is in user mode or privileged mode */ 00303 #define GPDMA_DMACCxControl_Prot2 (1UL << 29) /* Indicates that the access is bufferable or not bufferable */ 00304 #define GPDMA_DMACCxControl_Prot3 (1UL << 30) /* Indicates that the access is cacheable or not cacheable */ 00305 #define GPDMA_DMACCxControl_I (1UL << 31) /* Terminal count interrupt enable bit */ 00306 #define GPDMA_DMACCxControl_BITMASK 0xFCFFFFFF /* DMA channel control registers bit mask */ 00307 00308 00309 /*----------------------------------------------------------------------------* 00310 Macro defines for DMA Channel Configuration registers 00311 *----------------------------------------------------------------------------*/ 00312 00313 #define GPDMA_DMACCxConfig_E (1UL << 0) /* DMA control enable */ 00314 #define GPDMA_DMACCxConfig_SrcPeripheral(n) ((n & 0x1F) << 1) /* Source peripheral */ 00315 #define GPDMA_DMACCxConfig_DestPeripheral(n) ((n & 0x1F) << 6) /* Destination peripheral */ 00316 #define GPDMA_DMACCxConfig_TransferType(n) ((n & 0x7) << 11) /* This value indicates the type of transfer */ 00317 #define GPDMA_DMACCxConfig_IE (1UL << 14) /* Interrupt error mask */ 00318 #define GPDMA_DMACCxConfig_ITC (1UL << 15) /* Terminal count interrupt mask */ 00319 #define GPDMA_DMACCxConfig_L (1UL << 16) /* Lock */ 00320 #define GPDMA_DMACCxConfig_A (1UL << 17) /* Active */ 00321 #define GPDMA_DMACCxConfig_H (1UL << 18) /* Halt */ 00322 #define GPDMA_DMACCxConfig_BITMASK 0x7FFFF /* DMA Channel Configuration registers bit mask */ 00323 00324 00325 /*============================================================================* 00326 Type definitions 00327 *============================================================================*/ 00328 00329 /*----------------------------------------------------------------------------* 00330 GPDMA Status enumeration 00331 *----------------------------------------------------------------------------*/ 00332 00333 typedef enum { 00334 GPDMA_STAT_INT, /* GPDMA Interrupt Status */ 00335 GPDMA_STAT_INTTC, /* GPDMA Interrupt Terminal Count Request Status */ 00336 GPDMA_STAT_INTERR, /* GPDMA Interrupt Error Status */ 00337 GPDMA_STAT_RAWINTTC, /* GPDMA Raw Interrupt Terminal Count Status */ 00338 GPDMA_STAT_RAWINTERR, /* GPDMA Raw Error Interrupt Status */ 00339 GPDMA_STAT_ENABLED_CH /* GPDMA Enabled Channel Status */ 00340 } gpdma_status_t; 00341 00342 00343 /*----------------------------------------------------------------------------* 00344 GPDMA Interrupt clear status enumeration 00345 *----------------------------------------------------------------------------*/ 00346 00347 typedef enum{ 00348 GPDMA_STATCLR_INTTC, /* GPDMA Interrupt Terminal Count Request Clear */ 00349 GPDMA_STATCLR_INTERR /* GPDMA Interrupt Error Clear */ 00350 } gpdma_state_clear_t; 00351 00352 00353 /*----------------------------------------------------------------------------* 00354 GPDMA Channel configuration structure type definition 00355 *----------------------------------------------------------------------------*/ 00356 00357 typedef struct { 00358 uint32_t ch; /* DMA channel number, should be in 00359 range from 0 to 7. 00360 Note: DMA channel 0 has the highest priority 00361 and DMA channel 7 the lowest priority. 00362 */ 00363 00364 uint32_t transfer_size; /* Length/Size of transfer */ 00365 00366 uint32_t transfer_width;/* Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */ 00367 00368 uint32_t src_addr; /* Physical Source Address, used in case TransferType is chosen as 00369 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */ 00370 00371 uint32_t dst_addr; /* Physical Destination Address, used in case TransferType is chosen as 00372 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */ 00373 00374 uint32_t transfer_type; /* Transfer Type, should be one of the following: 00375 - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control 00376 - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control 00377 - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control 00378 - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control 00379 */ 00380 00381 uint32_t src_conn; /* Peripheral Source Connection type, used in case TransferType is chosen as 00382 GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of 00383 following: 00384 - GPDMA_CONN_SSP0_Tx: SSP0, Tx 00385 - GPDMA_CONN_SSP0_Rx: SSP0, Rx 00386 - GPDMA_CONN_SSP1_Tx: SSP1, Tx 00387 - GPDMA_CONN_SSP1_Rx: SSP1, Rx 00388 - GPDMA_CONN_ADC: ADC 00389 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 00390 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 00391 - GPDMA_CONN_DAC: DAC 00392 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 00393 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 00394 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 00395 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 00396 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 00397 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 00398 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 00399 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 00400 */ 00401 00402 uint32_t dst_conn; /* Peripheral Destination Connection type, used in case TransferType is chosen as 00403 GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of 00404 following: 00405 - GPDMA_CONN_SSP0_Tx: SSP0, Tx 00406 - GPDMA_CONN_SSP0_Rx: SSP0, Rx 00407 - GPDMA_CONN_SSP1_Tx: SSP1, Tx 00408 - GPDMA_CONN_SSP1_Rx: SSP1, Rx 00409 - GPDMA_CONN_ADC: ADC 00410 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 00411 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 00412 - GPDMA_CONN_DAC: DAC 00413 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 00414 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 00415 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 00416 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 00417 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 00418 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 00419 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 00420 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 00421 */ 00422 00423 uint32_t dma_lli; /* Linker list item structure data address 00424 if there's no linker list, set as '0' 00425 */ 00426 } gpdma_channel_cfg_t; 00427 00428 00429 /*----------------------------------------------------------------------------* 00430 GPDMA Linker List Item structure type definition 00431 *----------------------------------------------------------------------------*/ 00432 00433 typedef struct { 00434 uint32_t SrcAddr; /* Source Address */ 00435 uint32_t DstAddr; /* Destination address */ 00436 uint32_t NextLLI; /* Next LLI address, otherwise set to '0' */ 00437 uint32_t Control; /* GPDMA Control of this LLI */ 00438 } gpdma_lli_t; 00439 00440 00441 00442 void Lpc17xxGPDMA_Init(void); 00443 int Lpc17xxGPDMA_Setup(gpdma_channel_cfg_t *ch_config); 00444 int Lpc17xxGPDMA_IntGetStatus(gpdma_status_t type, uint8_t ch); 00445 void Lpc17xxGPDMA_ClearIntPending(gpdma_state_clear_t type, uint8_t ch); 00446 void Lpc17xxGPDMA_ChannelCmd(uint8_t ch, int enabled); 00447 00448 #endif /* _LPC17XX_GPDMA_H_ */