at91_mc.h

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#ifndef _ARCH_ARM_AT91_MC_H_
#define _ARCH_ARM_AT91_MC_H_

/*
 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 */

#define MC_RCR_OFF              0x00000000      
#define MC_RCR      (MC_BASE + MC_RCR_OFF)      
#define MC_RCB                  0x00000001      
#define MC_ASR_OFF              0x00000004      
#define MC_ASR      (MC_BASE + MC_ASR_OFF)      
#define MC_UNDADD               0x00000001      
#define MC_MISADD               0x00000002      
#define MC_ABTSZ_MASK           0x00000300      
#define MC_ABTSZ_BYTE           0x00000000      
#define MC_ABTSZ_HWORD          0x00000100      
#define MC_ABTSZ_WORD           0x00000200      
#define MC_ABTTYP_MASK          0x00000C00      
#define MC_ABTTYP_DATAR         0x00000000      
#define MC_ABTTYP_DATAW         0x00000400      
#define MC_ABTTYP_FETCH         0x00000800      
#define MC_MST_EMAC             0x00010000      
#define MC_MST_PDC              0x00020000      
#define MC_MST_ARM              0x00040000      
#define MC_SVMST_EMAC           0x01000000      
#define MC_SVMST_PDC            0x02000000      
#define MC_SVMST_ARM            0x04000000      
#define MC_AASR_OFF             0x00000008      
#define MC_AASR     (MC_BASE + MC_AASR_OFF)     
#define MC_FMR_EFC0_OFF         0x00000060      
#define MC_FMR_EFC0 (MC_BASE + MC_FMR_EFC0_OFF) 
#define MC_FMR_EFC1_OFF         0x00000070      
#define MC_FMR_EFC1 (MC_BASE + MC_FMR_EFC1_OFF) 
#define MC_FMR_OFF         MC_FMR_EFC0_OFF      
#define MC_FMR                 MC_FMR_EFC0      
#define MC_FRDY                 0x00000001      
#define MC_LOCKE                0x00000004      
#define MC_PROGE                0x00000008      
#define MC_NEBP                 0x00000080      
#define MC_FWS_LSB                       8      
#define MC_FWS_MASK             0x00000300      
#define MC_FWS_1R2W             0x00000000      
#define MC_FWS_2R3W             0x00000100      
#define MC_FWS_3R4W             0x00000200      
#define MC_FWS_4R4W             0x00000300      
#define MC_FMCN_LSB                     16      
#define MC_FMCN_MASK            0x00FF0000      
#define MC_FCR_EFC0_OFF         0x00000064      
#define MC_FCR_EFC0 (MC_BASE + MC_FCR_EFC0_OFF) 
#define MC_FCR_EFC1_OFF         0x00000074      
#define MC_FCR_EFC1 (MC_BASE + MC_FCR_EFC1_OFF) 
#define MC_FCR_OFF         MC_FCR_EFC0_OFF      
#define MC_FCR                 MC_FCR_EFC0      
#define MC_FCMD_MASK            0x0000000F      
#define MC_FCMD_NOP             0x00000000      
#define MC_FCMD_WP              0x00000001      
#define MC_FCMD_SLB             0x00000002      
#define MC_FCMD_WPL             0x00000003      
#define MC_FCMD_CLB             0x00000004      
#define MC_FCMD_EA              0x00000008      
#define MC_FCMD_SGPB            0x0000000B      
#define MC_FCMD_CGPB            0x0000000D      
#define MC_FCMD_SSB             0x0000000F      
#define MC_PAGEN_MASK           0x0003FF00      
#define MC_KEY                  0x5A000000      
#define MC_FSR_EFC0_OFF         0x00000068      
#define MC_FSR_EFC0 (MC_BASE + MC_FSR_EFC0_OFF) 
#define MC_FSR_EFC1_OFF         0x00000078      
#define MC_FSR_EFC1 (MC_BASE + MC_FSR_EFC1_OFF) 
#define MC_FSR_OFF         MC_FSR_EFC0_OFF      
#define MC_FSR                 MC_FSR_EFC0      
#define MC_SECURITY             0x00000010      
#define MC_GPNVM0               0x00000100      
#define MC_GPNVM1               0x00000200      
#define MC_GPNVM2               0x00000400      
#define MC_LOCKS0               0x00010000      
#define MC_LOCKS1               0x00020000      
#define MC_LOCKS2               0x00040000      
#define MC_LOCKS3               0x00080000      
#define MC_LOCKS4               0x00100000      
#define MC_LOCKS5               0x00200000      
#define MC_LOCKS6               0x00400000      
#define MC_LOCKS7               0x00800000      
#define MC_LOCKS8               0x01000000      
#define MC_LOCKS9               0x02000000      
#define MC_LOCKS10              0x04000000      
#define MC_LOCKS11              0x08000000      
#define MC_LOCKS12              0x10000000      
#define MC_LOCKS13              0x20000000      
#define MC_LOCKS14              0x40000000      
#define MC_LOCKS15              0x80000000      
#endif                          /* _ARCH_ARM_AT91_MC_H_ */